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ML561 manual
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140 pages, 9.81 Mb
R
Virtex-5 FPGA ML561
Memory Interfaces
Development Board
User Guide
UG199 (v1.2) April 19, 2008
Contents
Main
Revision History
The following table shows the revision history for this document.
Table of Contents
Preface: About This Guide
Chapter 1: Introduction
Chapter 2: Getting Started
Chapter 3: Hardware Description
Chapter 4: Electrical Requirements
Chapter 5: Signal Integrity Recommendations
Chapter 6: Configuration
Chapter 7: ML561 Hardware-Simulation Correlation
Appendix A: FPGA Pinouts
Appendix B: Bill of Materials Appendix C: LCD Interface
General Display Hardware Design Hardware Schematic Diagram
Page
Preface
About This Guide
Guide Contents
Additional Documentation
Additional Support Resources
Conventions
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
This document uses the following typographical conventions. An example illustrates each convention.
Online Document
Preface: About This Guide
Chapter 1
Introduction
About the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit
Virtex-5 FPGA ML561 Memory Interfaces Development Board
Page
Page
Chapter 2
Getting Started
Documentation and Reference Design CD
Initial Board Check Before Applying Power
Applying Power to the Board
Chapter 3
Hardware Description
Hardware Overview
FPGA
USB
VTT & VREF
FPGA #3
Figure 3-1: ML561 XC5VLX50T-FFG1136 Board Placement Diagram
Memories
DDR400 SDRAM Components
DDR2 DIMM
DDR2 SDRAM Components
QDRII SRAM
RLDRAM II Devices
Memory Details
DDR400 and DDR2 Component Memories
Figure 3-3: FPGA #1 Banks for DDR400 and DDR2 Component (Top View)
Page
DDR2 SDRAM DIMM
Figure 3-4: FPGA #2 Banks for DDR2 DIMM (SSTL18) Interfaces (Top View)
Table 3-5: DDR2 DIMM Signal Summary
QDRII and RLDRAM II Memories
Figure 3-5: FPGA #3 Banks for QDRII SRAM and RLDRAM II Interfaces (Top View)
Page
External Interfaces
RS-232
USB
Clocks
200 MHz LVPECL Clock
SMA Clock
33 MHz Clock
33 MHz System ACE Controller Oscillator
GTP Clocks
User I/Os
General-Purpose Headers
DIP Switch
Seven-Segment Displays
Light Emitting Diodes (LEDs)
Pushbuttons
Power On or Off Slide Switch
Soft Touch Probe Points
Power Measurement Header
Liquid Crystal Display Connector
Power Regulation
Figure 3-8: LCD Panel Connector for Possible LCD Support
Figure 3-9: Virtex-5 FPGA ML561 Development Board Power Distribution System
Power R egulati on
Power D istri bution
Voltage Regulators
PTH05010 Voltage Regulator
Page
Board Design Considerations
Page
Page
Chapter 4
Electrical Requirements
Power Consumption
Table 4-1: ML561 Power Consumption
Table 4-1: ML561 Power Consumption (Continued)
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Page
Page
Table 4-3: ML561 Power Plane Capacities (Continued)
FPGA Internal Power Budget
Chapter 5
Signal Integrity Recommendations
Termination and Transmission Line Summaries
Chapter 5: Signal Integrity Recommendations
Table 5-1: DDR400 SDRAM Component Terminations
Table 5-2: DDR2 SDRAM DIMM Terminations
Table 5-3: DDR2 SDRAM Component Terminations
Termination and Transmission Line Summaries
Table 5-4: QDRII SRAM Terminations
Table 5-5: RLDRAM II Terminations
Page
Chapter 6
Configuration
Configuration Modes
JTAG Chain
JTAG Port
Parallel IV Cable Port
System ACE Interface
System ACE Interface
Page
Chapter 7
ML561 Hardware-Simulation Correlation
Introduction
Test Setup
Page
Signal Integrity Correlation Results
DDR2 Component Write Operation
Figure 7-3: Post-Layout IBIS Schematics of DDR2 Component Write Data Bit (DDR2_DQ_BY2_B3)
Table 7-1: Circuit Elements of DDR2 Component Write Data Bit (DDR2_DQ_BY2_B3)
Table 7-2: DDR2 Component Write Operation Correlation Results
Page
Figure 7-4: DDR2 Component Write HW Measurement - Eye Scope Shot at Probe Point (DDR2 Memory Via)
Figure 7-5: DDR2 Component Write Correlation - Eye Scope Shot at Probe Point (Slow Corner)
Page
Figure 7-8: DDR2 Component Write Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
Figure 7-9: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
Virtex-5 FPGA ML561 User Guide www.xilinx.com 63
Figure 7-10: DDR2 Component Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
Figure 7-11: DDR2 Component Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
64 www.xilinx.com Virtex-5 FPGA ML561 User Guide
DDR2 Component Read Operation
Figure 7-12: Post-Layout IBIS Schematics of the DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)
Table 7-4: Circuit Elements of DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)
Table 7-5: DDR2 Component Read Operation Correlation Results
Figure 7-13: DDR2 Component Read HW Measurement - Eye Scope Shot at Probe Point (FPGA1 Via)
Figure 7-14: DDR2 Component Read Correlation - Eye Scope Shot at Probe Point (Slow Corner)
Page
Figure 7-17: DDR2 Component Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
Time (ns)
Figure 7-18: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
68 www.xilinx.com Virtex-5 FPGA ML561 User Guide
Figure 7-19: DDR2 Component Read Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
Figure 7-20: DDR2 Component Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
Virtex-5 FPGA ML561 User Guide www.xilinx.com 69
DDR2 DIMM Write Operation
UG199_c7_21_071907
Figure 7-21: Post-Layout IBIS Schematics of DDR2 DIMM Write Data Bit (DDR2_DIMM_DQ_BY2_B3)
Table 7-6: Circuit Elements of DDR2 DIMM Write Data Bit (DDR2_DIMM_DQ_BY2_B3)
Table 7-7: DDR2 DIMM Write Operation Correlation Results
Table 7-8: DIP[1:2] Settings
Figure 7-22: DDR2 DIMM Write HW Measurement - Eye Scope Shot at Probe Point #1 (DDR2 Memory Via)
Figure 7-23: DDR2 DIMM Write Correlation - Eye Scope Shot at Probe Point #1 (Slow Corner)
Page
Figure 7-26: DDR2 DIMM Write Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
Figure 7-27: DDR2 DIMM Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
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Figure 7-28: DDR2 DIMM Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
Figure 7-29: DDR2 DIMM Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
Virtex-5 FPGA ML561 User Guide www.xilinx.com 75
DDR2 DIMM Read Operation
Figure 7-30: Post-Layout IBIS Schematics of the DDR2 DIMM Read Data Bit (DDR2_DIMM_DQ_B)
Table 7-9: Circuit Elements of DDR2 DIMM Read Data Bit (DDR2_DIMM_DQ_BY2_B3)
Table 7-10: DDR2 DIMM Read Operation Correlation Results
Figure 7-31: DDR2 DIMM Read HW Measurement - Eye Scope Shot at Probe Point (FPGA1 Via)
Figure 7-32: DDR2 DIMM Read Correlation - Eye Scope Shot at Probe Point (Slow Corner)
Figure 7-33: DDR2 DIMM Read HW Measurement - Waveform Scope Shot at Probe Point (FPGA1 Via)
Figure 7-34: DDR2 DIMM Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
Figure 7-35: DDR2 DIMM Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
Figure 7-36: DDR2 DIMM Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
Virtex-5 FPGA ML561 User Guide www.xilinx.com 79
Figure 7-37: DDR2 DIMM Read Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
Figure 7-38: DDR2 DIMM Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
80 www.xilinx.com Virtex-5 FPGA ML561 User Guide
QDRII Write Operation
Figure 7-39: Post-Layout IBIS Schematics of QDRII Write Data Bit (QDR2_D_BY0_B5)
Table 7-11: Circuit Elements of QDRII Write Data bit (QDR2_D_BY0_B5)
Table 7-12: QDRII Write Operation Correlation Results
Figure 7-40: QDRII Write HW Measurement - Eye Scope Shot at Probe Point (QDRII Memory Via)
Figure 7-41: QDRII Write Correlation - Eye Scope Shot at Probe Point (Slow Corner)
Figure 7-42: QDRII Write HW Measurement - Waveform Scope Shot at Probe Point (QDRII Memory Via)
Figure 7-43: QDRII Write Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
Figure 7-44: QDRII Write Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
Figure 7-45: QDRII Write Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner)
84 www.xilinx.com Virtex-5 FPGA ML561 User Guide
Figure 7-46: QDRII Write Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
Figure 7-47: QDRII Write Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
Virtex-5 FPGA ML561 User Guide www.xilinx.com 85
QDRII Read Operation
Figure 7-48: Post-Layout IBIS Schematics of QDRII Read Data Bit (QDR2_Q_BY0_B5)
Table 7-13: Circuit Elements of QDRII Read Data Bit (QDR2_Q_BY0_B5)
Table 7-14: QDRII Read Operation Correlation Results
Figure 7-49: QDRII Read HW Measurement - Eye Diagram Scope Shot at Probe Point (FPGA3 Via)
Figure 7-50: QDRII Read Correlation - Eye Diagram Scope Shot at Probe Point (Slow Corner)
Figure 7-51: QDRII Read HW Measurement - Waveform Scope Shot at Probe Point (FPGA3 Via)
Figure 7-52: QDRII Read Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
Figure 7-53: QDRII Read Extrapolation - Eye Scope Shot at Receiver IOB (Slow Corner)
Figure 7-54: QDRII Read Extrapolation - Waveform Scope Shot at Receiver IOB (Slow Corner
Virtex-5 FPGA ML561 User Guide www.xilinx.com 89
Figure 7-55: QDRII Read Extrapolation - Eye Scope Shot at Receiver IOB (Fast Corner)
Figure 7-56: QDRII Read Extrapolation - Waveform Scope Shot at Receiver IOB (Fast Corner)
90 www.xilinx.com Virtex-5 FPGA ML561 User Guide
Summary and Recommendations
Page
How to Generate a User-Specific FPGA IBIS Model
Page
Appendix A
FPGA Pinouts
FPGA #1 Pinout
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FPGA #1 Pinout
FPGA #2 Pinout
Tabl e A-2 lists the connections for FPGA #2 (U5). Table A-2: FPGA #2 Pinout
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FPGA #3 Pinout
Tabl e A-3 lists the connections for FPGA #3 (U34). Table A-3: FPGA #3 Pinout
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Appendix B
Bill of Materials
Appendix B: Bill of Materials
Table B-1: Bill of Materials (Continued)
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Appendix C
LCD Interface
General
Display Hardware Design
Tabl e C-1 summarizes the controller specifications.
The on-chip RAM size is 65x 132 = 8580 bits.
Hardware Schematic Diagram
Tabl e C -1 : Display Controller Specifications
Peripheral Device KS0713
FigureC-2 is a block diagram of t he Samsung KS0713.
KS0713 Samsung
Figure C-2: KS0713 Block Diagram
Controller
Figure C-4: 64128EFCBC-XLP Dimensions
Figure C-3: 64128EFCBC-XLP Block Diagram
128 x 64 DOTS
FigureC-4 shows the dimensions for the 64128EFCBC-XLP LCD panel.
Controller Operation
Table C-2: LCD Panel (Continued)
Controller LCD Panel Connections
Table C-2: LCD Panel (Continued)
Controller Power Supply Circuits
Operation Example of the 64128EFCBC-3LP
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Instruction Set
Tabl e C-6 shows the instruction set for the LCD panel. Table C-6: Display Instructions
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Table C-6: Display Instructions (Continued)
Read/Write Characteristics (6800 Mode)
Figure C-7: Read/Write Timing Waveforms (6800 Mode)
Design Examples
LCD Panel Used in Full Graphics Mode
LCD Panel Used in Character Mode
Display Command Byte
Display Data Byte
Figure C-10: Block RAM Organization
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Array Connector Numbering