Xilinx manual Virtex-5 Fpga ML561 Memory Interfaces Development Board

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Virtex-5 FPGA ML561 Memory Interfaces Development Board

Figure 1-2shows the Virtex-5 FPGA ML561 Development Board and indicates the locations of the resident memory devices.

32-bit DDR400

144 bits wide

DDR2

SDRAM

DIMM

72 bits wide, up to 4 deep

36-bit

RLDRAM II

SDRAM

32-bit DDR2

SDRAM

72-bit

QDRII SRAM

UG199_c1_02_050106

Figure 1-2:Virtex-5 FPGA ML561 Development Board

Virtex-5 FPGA ML561 User Guide www.xilinx.com 13

UG199 (v1.2) April 19, 2008