Xilinx ML561 manual DDR2 Dimm Write Operation, DDR2 DIMM, 75 Ω ODT

Chapter 7: ML561 Hardware-Simulation Correlation

R

DDR2 DIMM Write Operation

This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from FPGA2 (U5) to the DDR2 DIMM (XP2) measured at 333 MHz (667 Mb/s), where the unit interval (UI) = 1.5 ns.

49.8 ohms

49.8 ohms

49.8 ohms

49.8 ohms

49.1 ohms

49.1 ohms

71.6 ohms

28.5 ohms

94.605 ps

90.955 ps

90.340 ps

864.365 ps

59.1 ohms

78.216 ps

41.316 ps

4.473 ps

U5_B00.H29

0.606 in

0.582 in

0.578 in

5.533 in

12.486 ps

0.501 in

0.264 in

22.319 ps

0.028 in

59.8 ohms

59.8 ohms

59.8 ohms

59.8 ohms

DDR2_DIMM_DQ_...

DDR2_DIMM_DQ_... DDR2_DIMM_DQ_...

DDR2_DIMM_DQ_...

AutoPadstk_12_B...

DDR2_DIMM_DQ_... DDR2_DIMM_DQ_... AutoPadstk_3_B00

DDR2_DIMM_DQ_...

3.590 ps

31.503 ps

78.962 ps

10.373 ps

U3_B01.J1

0.022 in

0.195 in

0.490 in

0.064 in

J1_B01.31

MDQ19_B01 MDQ19_B01 MDQ19_B01

RN6_B01

DQ19_B01

TL15

TL16

TL17

TL18

TL19

TL20

TL7

TL6

TL3

Virtex-5 FPGA

XP2_B00.31

XP3_B00.31

XP4_B00.31

XP5_B00.31

DDR2_DQ_BY2_B3

TL1

TL5

TL11

22.0 ohms

TL12

MT47H64M8CB_C...

????

DDR2_DI...

DDR2_DI...

DQ6

TL14

TL27

TL23

TL25

DDR2_DI...

DDR2_DI...

C8

MDQ19_...

C13

????

????

????

????

22.9 fF

		50.3 ohms	50.3 ohms	50.3 ohms	50.3 ohms	253.0 fF	96.3 fF	500.0 fF
		23.650 ps					46.4 fF
			23.650 ps	23.650 ps	23.650 ps
17.3 fF	500.0 fF	DDR2_D...
			DDR2_D...	DDR2_D...	DDR2_D...

R_00179...	R7	R5	R6
0.0 milliohms	0.0 milliohms	0.0 milliohms	0.0 milliohms
TL13	TL26	TL22	TL24
50.3 ohms
23.650 ps	50.3 ohms	50.3 ohms	50.3 ohms
DQ19_B...	23.650 ps	23.650 ps
			23.650 ps
	DQ19_B...	DQ19_B...
			DQ19_B...

UG199_c7_21_071907

Figure 7-21:Post-Layout IBIS Schematics of DDR2 DIMM Write Data Bit (DDR2_DIMM_DQ_BY2_B3)

Table 7-6:Circuit Elements of DDR2 DIMM Write Data Bit (DDR2_DIMM_DQ_BY2_B3)

Element	Designation	Description
Driver	U5.H29	FPGA SSTL18_II_DCI_O
Receiver	XP2-U3.J1	DDR2 DIMM, 75 Ω ODT
Probe Point	C13	Via under memory on DIMM
PCB Termination	None	ODT at load
Trace Length	Multiple TLs	8.975 inches

The IBIS schematics for DDR2 DIMM interface is extracted from a multi-board project definition of the two-board combination, which includes the ML561 motherboard and the DDR2 DIMM at the XP2 connector of the motherboard. The impedance characteristics of the Molex socket pin (XP2, pin 31) is also included in the IBIS model as a (TL13, R_00179_CONN_0001, TL14) combination.

The ML561 board under test (S/N 103) is assembled with DDR2 sockets XP3, XP4, and XP5, which can be utilized for deep DIMM interfaces as described in Table 3-2, page 19 and Figure 3-2, page 20. To accurately represent the IBIS model of the DDR2_DIMM_DQ_BY2_B3 signal, the IBIS schematics in Figure 7-21have added stubs for the three socket pins at the XP3, XP4, and XP5 connectors.

The DDR2 DIMM used for this correlation testing is a single-rank DIMM part (Micron part number MT9HTF6472xx-667). Thus for hardware measurements closest to the load, a probe point via on the DIMM for pin U3.J1 is available.

70 www.xilinx.com Virtex-5 FPGA ML561 User Guide

UG199 (v1.2) April 19, 2008