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Xilinx ML561 manual Controller Operation, Table C-2 LCD Panel

Models: ML561

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Hardware Schematic Diagram

Controller – Operation

The pixels for the LCD panel are stored in the controller data RAM. This RAM is a 65-row by 132-column array. Each display pixel is represented by a single bit in the RAM array.

The interface to the RAM array goes through the 8-bit (DB0 – DB7) LCD interface. Therefore, the 65-bit rows are split into eight pages of eight lines. The ninth page is a single line page (DB0 only).

Interface designs can read from or write to the RAM array.

The display page is changed through the 4-bit page address register.

The column address (line address) is set with a two-byte register access. The line address corresponds to the first line that is going to be displayed on the LCD panel. This address is located in a 6-bit address register.

The RAM array is configured such that there are two characters per row (page), where each character pair uses eight rows of the display panel. Table C-2shows the input data bytes, address lines, ADC control, and LCD outputs (segments).

Table C-2: LCD Panel

DB3

DB2

DB1

DB0

Data

Line

Address

DB0

00H

DB1

01H

DB2

02H

0

0

0

0

DB3

Page 0

03H

DB4

04H

DB5

05H

DB6

06H

DB7

07H

DB0

08H

DB1

09H

DB2

0AH

0

0

0

1

DB3

Page 1

0BH

DB4

0CH

DB5

0DH

DB6

0EH

DB7

0FH

Virtex-5 FPGA ML561 User Guide

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UG199 (v1.2) April 19, 2008

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Xilinx ML561 manual Controller Operation, Table C-2 LCD Panel

Contents

UG199 v1.2 April 19 Virtex-5 Fpga ML561 Memory Interfaces Development BoardDate Version Revision Revision HistoryTable of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide Guide Contents About This GuideAdditional Documentation Preface About This Guide Additional Support ResourcesOnline Document ConventionsTerminology TypographicalVirtex-5 Fpga ML561 User Guide About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit IntroductionIntroduction Virtex-5 Fpga ML561 Memory Interfaces Development Board2Virtex-5 Fpga ML561 Development Board Virtex-5 Fpga ML561 Memory Interfaces Development BoardIntroduction Initial Board Check Before Applying Power Getting StartedDocumentation and Reference Design CD Getting Started Applying Power to the BoardHardware Overview Hardware DescriptionHardware Description 1ML561 XC5VLX50T-FFG1136 Board Placement DiagramMemories DDR400 Sdram ComponentsHardware Overview Rldram II Devices DDR2 Sdram ComponentsMemory Details DDR400 and DDR2 Component MemoriesMemory Details DDR2ODT10, DDR2RAS,CAS,WEN DDR1RAS,CAS,WEN, DDR1CKEDDR2 Sdram Dimm DDR2DIMM15CNTLPARERR DDR2DIMMRAS,CAS,WE,RESETNDimm DDR2DIMM15CNTLPARQdrii and Rldram II Memories QDR2R,W,DLLOFFN External Interfaces RS-232Clocks MHz Lvpecl Clock SMA ClockMHz Clock GTP Clocks DIP SwitchUser I/Os MHz System ACE Controller OscillatorPushbuttons Seven-Segment Display Signal MappingSeven-Segment Displays Light Emitting Diodes LEDsPower On or Off Slide Switch Power Measurement HeaderSoft Touch Probe Points Liquid Crystal Display Connector Power Regulation Power DistributionPower Regulation 10PTH05010 Voltage Regulator Voltage RegulatorsOutput Voltage 16Manual Voltage MarginingBoard Design Considerations 11ML561 Revision a PCB Stack-Up Board Design ConsiderationsTOP 19ML561 Revision a PCB Controlled ImpedanceElectrical Requirements Power ConsumptionCurrent Total Available PowerPower Consumed DDR400 Component Interface Total Power ConsumedPower Modules Capacity 2Power Planes Voltage Regulator Module VRM Part Electrical RequirementsStack-Up Power Consumed by Power Plane Power Consumption3ML561 Power Plane Capacities Current Power Excess Device Description QuantityElectrical Requirements 3ML561 Power Plane Capacities Power Consumption 3ML561 Power Plane Capacities Current Power Excess Device DescriptionTotal Power Consumed 53.2 Fpga Internal Power Budget 4ML561 Fpga Power Estimate SummaryFpga #21 Termination and Transmission Line Summaries Signal Integrity Recommendations2DDR2 Sdram Dimm Terminations Signal Fpga Driver HSTLIIDCI18 5RLDRAM II Terminations SignalHSTLI18 HSTLIDCI18Signal Integrity Recommendations Configuration Modes ConfigurationParallel IV Cable Port Configuration 1Configuration ModesJtag Chain Jtag PortSystem ACE Interface Configuration Introduction ML561 Hardware-Simulation CorrelationML561 Hardware-Simulation Correlation Test Setup1Single Trapezoid Eye Mask Definition Test Setup2Two Triangular Eye Mask Definitions for VIH and VIL Signal Integrity Correlation ResultsMeasurement Signal Integrity Correlation ResultsDDR2 Component Write Operation 2DDR2 Component Write Operation Correlation Results3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 DDR2 Component Read Operation Fpga SSTL18IIDCII5DDR2 Component Read Operation Correlation Results Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 DIMM, 75 Ω ODT DDR2 Dimm Write OperationNoise Margin Overshoot / Undershoot Measurement 8DIP12 Settings DescriptionUG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 10DDR2 Dimm Read Operation Correlation Results DVW % DDR2 Dimm Read OperationUG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 Qdrii Write Operation Fpga HSTLI1812 Qdrii Write Operation Correlation Results 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 Qdrii Read Operation Fpga HSTLIDCI1814QDRII Read Operation Correlation Results UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Summary and Recommendations Summary and RecommendationsNoise Margin Overshoot Operation 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis ModelML561 Hardware-Simulation Correlation Fpga #1 Pinout Fpga PinoutsTable A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA3TOFPGA1MIITXDATA0 FPGA2TOFPGA1MIITXCLKFPGA3TOFPGA1MIITXCLK FPGA2TOFPGA1MIITXDATA0Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMMDQBY0B5 DDR2DIMM3CK2PDDR2DIMMDQBY0B4 DDR2DIMM3CKE0DDR2DIMMDQCB07B0 DDR2DIMMDQBY4B4DDR2DIMMDQBY7B7 DDR2DIMMDQBY4B5DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7 DDR2DIMM5CS0NDDR2DIMMDQBY11B5 DDR2DIMM5CS1N DDR2DIMMDQBY11B6Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal NameFPGA2SPYHOLEBK15 FPGA2DIP0FPGA2SOFTTOUCHBY1B7 FPGA2DIP1FPGA2TXP1BK120 FPGA2USBRSTN FPGA2TXN0BK120 FPGA2USBCTSNFPGA2TXN1BK120 FPGA2USBDSRN FPGA2TXP0BK120 FPGA2USBDTRNFpga #3 Pinout Table A-3FPGA #3 Pinout Signal Name Qdrii Memory InterfaceQDR2DBY4B2 QDR2DBY0B5QDR2DBY4B1 QDR2DBY0B6QDR2QBY3B3 QDR2DBY7B6QDR2QBY3B2 QDR2DBY7B7QDR2QBY7B5 QDR2QBY6B7QDR2QBY7B4 QDR2QBY6B8RLD2DQBY0B3 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0RLD2DBY0B7 RLD2DQBY0B1 RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0CLKTOFPGA3MGTP EXTCLKTOFPGA3P FPGA3RESETNINRLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6 CLKTOFPGA3MGTN EXTCLKTOFPGA3NTable A-3FPGA #3 Pinout Signal Name Table B-1Bill of Materials Bill of Materials4A LDO Appendix B Bill of Materials Table B-1Bill of MaterialsVirtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials LCD Interface GeneralDisplay Hardware Design Hardware Schematic Diagram Table C-1Display Controller Specifications ParameterAppendix C LCD Interface Peripheral Device KS0713 Hardware Schematic Diagram64128EFCBC-XLP Block Diagram Table C-2 LCD Panel Controller Operation124 Controller LCD Panel Connections Figure C-5Power Supply Circuits Controller Power Supply CircuitsFigure C-6LCD Controller Initialization Flow Operation Example of the 64128EFCBC-3LPOFF Table C-4Resistor Value Settings Table C-5 Reference Voltage ParametersReference Voltage Parameter α Table C-6Display Instructions Instruction SetSet page address Hardware Schematic Diagram Table C-6Display InstructionsEON Appendix C LCD Interface Table C-6Display InstructionsERD Read/Write Characteristics 6800 ModeDesign Examples LCD Panel Used in Full Graphics ModeDisplay Command Byte LCD Panel Used in Character ModeDisplay Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller C D E F G H Array Connector Numbering140