Xilinx ML561 manual 10DDR2 Dimm Read Operation Correlation Results DVW %

Chapter 7: ML561 Hardware-Simulation Correlation

R

DDR2 DIMM Read Operation

This subsection shows the test results for the DDR2_DIMM_DQ_BY2_B3 signal from the DDR2 DIMM (XP2) to FPGA2 (U5) measured at 333 MHz (667 Mb/s), where the unit interval (UI) = 1.5 ns.

	59.8 ohms	59.8 ohms	59.8 ohms	59.8 ohms
	3.590 ps	31.503 ps	78.962 ps	10.373 ps
U3_B01.J1	0.022 in	0.195 in	0.490 in	0.064 in
	MDQ19_B01

49.8 ohms

94.605 ps

0.606 in

DDR2_DIMM_DQ_...

J1_B01.31

49.8 ohms	49.8 ohms	49.8 ohms		49.1 ohms	49.1 ohms	71.6 ohms	28.5 ohms
90.955 ps	90.340 ps	864.365 ps	59.1 ohms	78.216 ps	41.316 ps		4.473 ps
0.582 in	0.578 in	5.533 in	12.486 ps	0.501 in	0.264 in	22.319 ps	0.028 in	U5_B00.H29
DDR2_DIMM_DQ_...	DDR2_DIMM_DQ_...	DDR2_DIMM_DQ_...	AutoPadstk_12_B...	DDR2_DIMM_DQ_...	DDR2_DIMM_DQ_...	AutoPadstk_3_B00	DDR2_DIMM_DQ_...

	MDQ19_B01 MDQ19_B01 RN6_B01			DQ19_B01
TL1	TL5	TL11	22.0 ohms	TL12
MT47H64M8CB_C...
DQ6
	MDQ19_...	C13
	17.3 fF	500.0 fF

TL15

XP2_B00.31

????

TL14

????

50.3 ohms 23.650 ps DDR2_D...

R_00179...

0.0 milliohms

TL13

50.3 ohms

23.650 ps DQ19_B...

TL16	TL17	TL18	TL19	TL20	TL7
XP3_B00.31	XP4_B00.31	XP5_B00.31
TL27	TL23	TL25	DDR2_DI...	DDR2_DI...
????	????	????
50.3 ohms	50.3 ohms	50.3 ohms	253.0 fF	46.4 fF
23.650 ps	23.650 ps	23.650 ps
DDR2_D...	DDR2_D...	DDR2_D...
R7	R5	R6
0.0 milliohms	0.0 milliohms	0.0 milliohms
TL26	TL22	TL24
50.3 ohms	50.3 ohms	50.3 ohms
23.650 ps	23.650 ps
		23.650 ps
DQ19_B...	DQ19_B...
		DQ19_B...

TL6	TL3
	Virtex-5 FPGA
	DIMM_DQ_BY2_B3

DDR2_DI...

DDR2_DI... C8

96.3 fF 500.0 fF 22.9 fF

UG199_c7_30_071907

Figure 7-30:Post-Layout IBIS Schematics of the DDR2 DIMM Read Data Bit (DDR2_DIMM_DQ_B)

Table 7-9:Circuit Elements of DDR2 DIMM Read Data Bit (DDR2_DIMM_DQ_BY2_B3)

	Element			Designation				Description
	Driver			XP2-U3.J1			DDR2 DIMM
	Receiver			U5.H29			FPGA SSTL18_II_DCI_I
	Probe Point			C8			Via under FPGA2 (U5.H29)
	PCB Termination			None			DCI at load
	Trace Length			Multiple TLs			8.975 inches
Table 7-10:DDR2 DIMM Read Operation Correlation Results
	DVW (%		ISI			Noise Margin		Overshoot / Undershoot
Measurement					(VIH + VIL) = Total			Margin
	UI)		(% UI)
						(% of VREF)		(% of VREF)
Hardware at probe	904 ps	(107 + 62) = 169 ps			(242 + 258) = 500 mV			(623 + 613) = 1236 mV
point	(60%)		(11.2%)					(137.3%)
Simulation correlation	865 ps	(130 + 83) = 213 ps			(+292 + 298) = 590 mV			(524 + 504) = 1028 mV
slow-weak corner	(59%)		(14.2%)					(114.2%)
Correlation Delta:	39 ps	44 ps (2.9%)				90 mV (10%)		208 mV (23.1%)
HW vs. Simulation	(2.6%)
Extrapolation at IOB	1.23 ns	(139 + 75) = 224 ps			(243 + 303) = 546 mV			(594 + 544) = 1138 mV
slow-weak corner	(82%)		(14.9%)			(60.7%)		(116.5%)
Extrapolation at IOB	1.24 ns	(131 + 60) = 191 ps			(288 + 282) = 570 mV			(+481 + 508) = 989 mV
fast-strong corner	(83%)		(12.7%)			(63.3%)		(109.9%)

To perform hardware measurements for a Read operation that is not interrupted by a Write or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch (SW1) setting:

•DIP[1:2] = 2’b10 – Write once, then Read only, Refresh disabled

76	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008