![](/images/new-backgrounds/1266586/26658619x1.webp)
Preface: About This Guide
R
Hardware Measurements
Noise Margin
Overshoot / Undershoot Margin
Simulation Correlation
These measurements are the actual
As the frequency of operation increases, the signal delay is affected by the data pattern that precedes the current data bit. This is called the
•Sum of ISI at
•Sum of ISI at
This is the noise margin available at the receiver. Measurements are taken at the AC voltage levels as the minimum vertical opening of the eye in the vicinity of the center of the bit period. Ideally, the input voltage needs to remain above the DC voltage specifications. However, by considering the AC voltage specifications for the nominal voltage level for VREF, these measurements are more conservative values that also include the effects of VREF variations.
•VIH margin: Difference between the top of the eye opening and
•VIL margin: Difference between
These measurements are performed in
Overshoot margin is the difference between the maximum allowable VIH per JEDEC specification and the maximum amplitude of the measured eye. Similarly, undershoot margin is the difference between the minimum amplitude of the measured eye and the minimum allowable VIL value per JEDEC specification. For both SSTL18 and 1.8V HSTL specifications:
•VIH(max) < (VDDQ + 300 mV) = (1.8 + 0.3)V = 2.1V
•VIL(min) >
The BoardSim utility of the HyperLynx simulator is used to extract the IBIS schematics of the same signal net for which hardware measurements are made. To replicate the hardware measurement probe set up at the probe point, a 0.5 pF probe capacitance is added based on Agilent probe loading specifications to the extracted IBIS schematics of the memory signal. For the FPGA devices soldered on the ML561 board under test, the process corner (slow, typical, or fast) is not known. Thus simulation is performed for all three corners
This term is the minimum input level at which the receiver must recognize input logic High.
When the input signal reaches
This term is the maximum input level at which the receiver must recognize input logic Low.
When the input signal reaches
10 | www.xilinx.com |
|
|
| UG199 (v1.2) April 19, 2008 |