Xilinx ML561 manual 2DDR2 Sdram Dimm Terminations Signal Fpga Driver

Chapter 5: Signal Integrity Recommendations

Table 5-1:DDR400 SDRAM Component Terminations

R

				Signal				FPGA Driver	Termination at FPGA	Termination at Memory
Data (DQ)								SSTL2_II_DCI	No termination	50Ω pull-up to 1.3V
Data Strobe (DQS)								SSTL2_II_DCI	No termination	50Ω pull-up to 1.3V
Clock (CK,								SSTL2_II	No termination	100Ω differential termination
		CK)
										between pair
Address (A, BA)								SSTL2_II	No termination	50Ω pull-up to 1.3V after the last
										component
Control							DM, and	SSTL2_II	No termination	50Ω pull-up to 1.3V after the last
	(RAS,		CAS,		WE,	CS,
CKE)										component

Table 5-2:DDR2 SDRAM DIMM Terminations

		Signal					FPGA Driver	Termination at FPGA	Termination at Memory
Data (DQ)							SSTL18_II_DCI	No termination	No termination (use 75Ω ODT(1))
Data Strobe (DQS,							DIFF_SSTL18_II_DCI	No termination	No termination (use 75Ω ODT)
				DQS)
Data Mask (DM)							SSTL18_II	No termination	No termination (use 75Ω ODT)
6 Pairs of Clocks (CK,							SSTL18_II	No termination	No termination(2)
						CK),
3 each per DIMM
Address (A, BA)							SSTL18_II	No termination	50Ω pull-up to 0.9V after the second
									DIMM
Control							SSTL18_II	No termination	50Ω pull-up to 0.9V after the second
		(RAS,	CAS,		WE,
CS,	CKE, and others)								DIMM

Notes:

1.Due to use of DCI I/O for DQ and DQS, these signals have parallel termination at the source during Write operations. Simulation results show that use of a weaker 75Ω ODT instead of a matching 50Ω ODT setting gives better noise margin at the memory.

2.The DIMM already contains 120Ω differential termination. A 5 pF capacitive termination is provided on the board as per Micron TN-47-01.

Table 5-3:DDR2 SDRAM Component Terminations

	Signal						FPGA Driver	Termination at FPGA	Termination at Memory
Data (DQ)							SSTL18_II_DCI	No termination	No termination (use 75Ω ODT)
Data Strobe (DQS,							DIFF_SSTL18_II_DCI	No termination	No termination (use 75Ω ODT)
				DQS)
Data Mask (DM)							SSTL18_II	No termination	No termination (use 75Ω ODT)
Clock (CK,							SSTL18_II	No termination	100Ωdifferential termination between
		CK)
									pair
Address (A, BA)							SSTL18_II	No termination	50Ω pull-up to 0.9V after the last
									component
Control							SSTL18_II	No termination	50Ω pull-up to 0.9V after the last
	(RAS,		CAS,		WE,	CS,
and CKE)									component

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		UG199 (v1.2) April 19, 2008