R
Chapter 2
Getting Started
This chapter describes the items needed to configure the Virtex-5 FPGA ML561 Memory Interfaces Development Board. The Virtex-5 FPGA ML561 Development Board is tested at the factory after assembly and should be received in working condition. It is set up to load a bitstream from the CompactFlash card at socket J27 through the System ACE controller (U45).
This chapter contains the following sections:
•“Documentation and Reference Design CD”
•“Initial Board Check Before Applying Power”
•“Applying Power to the Board”
Documentation and Reference Design CD
The CD included in the Virtex-5 FPGA ML561 Memory Interfaces Tool Kit contains the design files for the Virtex-5 FPGA ML561 Development Board, including schematics, board layout, and reference design files. Open the ReadMe.rtf file on the CD to review the list of contents.
Initial Board Check Before Applying Power
Perform these steps before applying board power:
1.Set up the Configuration Mode jumpers (P27, P46, and P112) for JTAG configuration.
See “Configuration Modes” on page 51 for all available modes for the Virtex-5 FPGA ML561 Development Board.
2.Confirm that the JTAG chain jumpers P38, P44, and P109 are connecting pins 1 to 2 and pins 3 to 4. This way, all three devices are in the chain. Otherwise, the ISE iMPACT software will not find all three devices to configure. For more information see “JTAG Chain” on page 52.
3.Make sure that no inhibit jumpers are present on any of the power supply regulator modules. For more information, see “Voltage Regulators” on page 34.
4.The Virtex-5 FPGA ML561 Development Board has a 200 MHz on-board oscillator, which provides a copy of a differential LVPECL clock to each of the three FPGAs through a differential clock buffer (ICS853006). There is also a connection to a pair of SMA connectors (J19, J20) to provide a differential LVDS clock from an off-board signal generator. Another differential clock buffer (ICS853006) provides a copy of this clock to each of the three FPGAs. These clocks are available after configuration for the design to use for various system clocks.
Virtex-5 FPGA ML561 User Guide | www.xilinx.com | 15 |
UG199 (v1.2) April 19, 2008
