Xilinx ML561 Qdrii Read Operation, Fpga HSTLIDCI18, 14QDRII Read Operation Correlation Results

Chapter 7: ML561 Hardware-Simulation Correlation

R

QDRII Read Operation

This subsection shows the test results for the QDR2_Q_BY0_B5 signal from QDRII memory (U35) to FPGA3 (U34) measured at 300 MHz (600 Mb/s), where the unit interval (UI) = 1.67 ns.

	28.5 ohms
	4.473 ps	71.6 ohms
U34.G33	0.028 in	22.319 ps
	QDR2_Q_BY0_B5	AutoPadstk_3
	TL1	TL2
Virtex-5 FPGA
QDR2_Q_BY0_B5
		QDR2_Q...
		22.9 fF

49.1 ohms

95.834 ps

0.613 in

QDR2_Q_BY0_B5

TL3

QDR2_Q...
	C7
96.3 fF	500.0 fF

		49.1 ohms		71.8 ohms
		427.654 ps
		2.737 in		22.319 ps
		QDR2_Q_BY0_B5 AutoPad...
	TL6			TL7
QDR2_Q...			QDR2_Q...
513.2 fF			96.3 fF

28.5 ohms
4.404 ps
0.027 in	U35.F11
QDR2_Q_BY0_B5

TL8

K7R323684M_1.8V C5

QDR2_Q...

22.9 fF

UG199_c7_48_071907

Figure 7-48:Post-Layout IBIS Schematics of QDRII Read Data Bit (QDR2_Q_BY0_B5) Table 7-13:Circuit Elements of QDRII Read Data Bit (QDR2_Q_BY0_B5)

		Element			Designation				Description
	Driver				U36.F11			QDRII memory
	Receiver				U34.G33			FPGA HSTL_I_DCI_18
	Probe Point				C7			Via under FPGA3 (U34)
	PCB Termination				None			DCI at FPGA
	Trace Length				TL 1, 3, 6, 8			3.41 inches
Table 7-14:QDRII Read Operation Correlation Results
	DVW			ISI			Noise Margin		Overshoot / Undershoot
Measurement							(VIH + VIL) = Total		Margin
	(% UI)			(% UI)
							(% of VREF)		(% of VREF)
Hardware at probe point	1.09 ns		(70 + 50) = 120 ps (7.2%)			(400 + 400) = 800 mV			(500 + 500) = 1000 mV
	(65.4%)						(88.9%)		(111.1%)
Simulation correlation	984 ps		(72 + 75) = 147 ps (8.8%)			(250 + 264) = 514 mV			(532 + 518) = 1050 mV
slow-weak corner	(59.0%)						(57.1%)		(105.5%)
Correlation Delta:	106 ps		27 ps (1.6%)				386 mV (31.8%)		50 mV (5.6%)
HW vs. Simulation	(6.4%)
Extrapolation at IOB	1.46 ns		(49 + 36) = 85 ps (5.1%)			(237 + 272) = 509 mV			(608 + 575) = 1183 mV
slow-weak corner	(88%)						(56.5%)		(131.5%)
Extrapolation at IOB	1.45 ns		(27 + 39) = 66 ps (4.0%)				(341 +201) = 542 mV		(532 + 661) = 1193 mV
fast-strong corner	(87%)						(60.3%)		(132.6%)

86	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008