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Appendix C: LCD Interface

R

•The voltage follower and voltage regulator are set to:

♦Five times boost mode

♦The V4, V3, V2, V1, and V0 outputs depend on the bias settings of 1/9 or 1/7. Because of these default settings, the following display controller connections are not used:

•DISP: Turns into an output when Master mode is selected

•FRS: Static driver segment output

•M: Used in Master/Slave display configurations

•CL: Clock pin used in Master/Slave display configurations

When RESETB is Low, the display controller is initialized as indicated in Table C-3.

Table C-3:Display Controller Initialization (RESETB is Low)

Parameter	Initial Value

Display	OFF

Entire Display	OFF

ADC Select	OFF

Reverse Display	OFF

Power Control	0,0,0 (VC, VR, VF)

LCD Bias	1/7

Read-Modify-Write	OFF

SHL Select	OFF

Static Indicator Mode	OFF

Static Indicator Register	0,0 (S1, S0)

Display Start	0 (First line)

Column Address	0

Page Address	0

Regulator Select	0,0,0 (R2, R1, R0)

Reference Voltage	OFF

Reference Voltage Register	1,0,0,0,0,0 (SV5, SV4, SV3, SV2, SV1, SV0)

When RESETB is High, the display must be initialized. The first steps to be taken to guarantee correct operation of the display and the controller are:

•Configure the ADC bit. This bit determines the scanning direction of the segments.

♦When the RESETB signal is active, ADC is reset to 0, meaning that the segments are scanned from SEG1 up to SEG132.

♦When ADC is set to 1, the segments are scanned in opposite direction.

•Configure the SHL bit. This bit sets the scanning direction of the COM lines.

♦When the RESETB signal is active, SHL is reset to 0, meaning that the segments are scanned from COM1 up to COM64.

♦When SHL is set to 1, the common lines are scanned in opposite direction.

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Contents

Virtex-5 Fpga ML561 Memory Interfaces Development Board UG199 v1.2 April 19 Revision History Date Version Revision Table of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide Additional Documentation Guide ContentsAbout This Guide Additional Support Resources Preface About This Guide Conventions TerminologyTypographical Online Document Virtex-5 Fpga ML561 User Guide Introduction About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit Virtex-5 Fpga ML561 Memory Interfaces Development Board Introduction Virtex-5 Fpga ML561 Memory Interfaces Development Board 2Virtex-5 Fpga ML561 Development Board Introduction Documentation and Reference Design CD Initial Board Check Before Applying PowerGetting Started Applying Power to the Board Getting Started Hardware Description Hardware Overview 1ML561 XC5VLX50T-FFG1136 Board Placement Diagram Hardware Description Hardware Overview MemoriesDDR400 Sdram Components DDR2 Sdram Components Rldram II Devices Memory Details Memory DetailsDDR400 and DDR2 Component Memories DDR1RAS,CAS,WEN, DDR1CKE DDR2ODT10, DDR2RAS,CAS,WEN DDR2 Sdram Dimm DDR2DIMMRAS,CAS,WE,RESETN DimmDDR2DIMM15CNTLPAR DDR2DIMM15CNTLPARERR Qdrii and Rldram II Memories QDR2R,W,DLLOFFN Clocks External InterfacesRS-232 MHz Clock MHz Lvpecl ClockSMA Clock DIP Switch User I/OsMHz System ACE Controller Oscillator GTP Clocks Seven-Segment Display Signal Mapping Seven-Segment DisplaysLight Emitting Diodes LEDs Pushbuttons Soft Touch Probe Points Power On or Off Slide SwitchPower Measurement Header Liquid Crystal Display Connector Power Regulation Power RegulationPower Distribution Voltage Regulators 10PTH05010 Voltage Regulator 16Manual Voltage Margining Output Voltage Board Design Considerations Board Design Considerations 11ML561 Revision a PCB Stack-Up 19ML561 Revision a PCB Controlled Impedance TOP Power Consumption Electrical Requirements Total Available Power Power Consumed DDR400 Component InterfaceTotal Power Consumed Current Power Modules Capacity Stack-Up 2Power Planes Voltage Regulator Module VRM PartElectrical Requirements Power Consumption 3ML561 Power Plane CapacitiesCurrent Power Excess Device Description Quantity Power Consumed by Power Plane Electrical Requirements 3ML561 Power Plane Capacities Total Power Consumed 53.2 Power Consumption 3ML561 Power Plane CapacitiesCurrent Power Excess Device Description Fpga #21 Fpga Internal Power Budget4ML561 Fpga Power Estimate Summary Signal Integrity Recommendations Termination and Transmission Line Summaries 2DDR2 Sdram Dimm Terminations Signal Fpga Driver 5RLDRAM II Terminations Signal HSTLI18HSTLIDCI18 HSTLIIDCI18 Signal Integrity Recommendations Configuration Configuration Modes Configuration 1Configuration Modes Jtag ChainJtag Port Parallel IV Cable Port System ACE Interface Configuration ML561 Hardware-Simulation Correlation Introduction Test Setup ML561 Hardware-Simulation Correlation Test Setup 1Single Trapezoid Eye Mask Definition Signal Integrity Correlation Results 2Two Triangular Eye Mask Definitions for VIH and VIL Signal Integrity Correlation Results DDR2 Component Write Operation2DDR2 Component Write Operation Correlation Results Measurement 3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 5DDR2 Component Read Operation Correlation Results DDR2 Component Read OperationFpga SSTL18IIDCII Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 Dimm Write Operation DDR2 DIMM, 75 Ω ODT 8DIP12 Settings Description Noise Margin Overshoot / Undershoot Measurement UG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 DDR2 Dimm Read Operation 10DDR2 Dimm Read Operation Correlation Results DVW % UG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 12 Qdrii Write Operation Correlation Results Qdrii Write OperationFpga HSTLI18 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 14QDRII Read Operation Correlation Results Qdrii Read OperationFpga HSTLIDCI18 UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Noise Margin Overshoot Operation Summary and RecommendationsSummary and Recommendations 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis Model ML561 Hardware-Simulation Correlation Fpga Pinouts Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA2TOFPGA1MIITXCLK FPGA3TOFPGA1MIITXCLKFPGA2TOFPGA1MIITXDATA0 FPGA3TOFPGA1MIITXDATA0 Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMM3CK2P DDR2DIMMDQBY0B4DDR2DIMM3CKE0 DDR2DIMMDQBY0B5 DDR2DIMMDQBY4B4 DDR2DIMMDQBY7B7DDR2DIMMDQBY4B5 DDR2DIMMDQCB07B0 DDR2DIMM5CS0N DDR2DIMMDQBY11B5 DDR2DIMM5CS1NDDR2DIMMDQBY11B6 DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7 Table A-2FPGA #2 Pinout Signal Name Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals FPGA2DIP0 FPGA2SOFTTOUCHBY1B7FPGA2DIP1 FPGA2SPYHOLEBK15 FPGA2TXN0BK120 FPGA2USBCTSN FPGA2TXN1BK120 FPGA2USBDSRNFPGA2TXP0BK120 FPGA2USBDTRN FPGA2TXP1BK120 FPGA2USBRSTN Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface Fpga #3 Pinout QDR2DBY0B5 QDR2DBY4B1QDR2DBY0B6 QDR2DBY4B2 QDR2DBY7B6 QDR2QBY3B2QDR2DBY7B7 QDR2QBY3B3 QDR2QBY6B7 QDR2QBY7B4QDR2QBY6B8 QDR2QBY7B5 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0 RLD2DBY0B7 RLD2DQBY0B1RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 RLD2DQBY0B3 FPGA3RESETNIN RLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6CLKTOFPGA3MGTN EXTCLKTOFPGA3N CLKTOFPGA3MGTP EXTCLKTOFPGA3P Table A-3FPGA #3 Pinout Signal Name Bill of Materials Table B-1Bill of Materials Appendix B Bill of Materials Table B-1Bill of Materials 4A LDO Virtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials Display Hardware Design LCD InterfaceGeneral Appendix C LCD Interface Hardware Schematic DiagramTable C-1Display Controller Specifications Parameter Hardware Schematic Diagram Peripheral Device KS0713 64128EFCBC-XLP Block Diagram Controller Operation Table C-2 LCD Panel 124 Controller LCD Panel Connections Controller Power Supply Circuits Figure C-5Power Supply Circuits Operation Example of the 64128EFCBC-3LP Figure C-6LCD Controller Initialization Flow OFF Reference Voltage Parameter α Table C-4Resistor Value SettingsTable C-5 Reference Voltage Parameters Instruction Set Table C-6Display Instructions Hardware Schematic Diagram Table C-6Display Instructions Set page address Appendix C LCD Interface Table C-6Display Instructions EON Read/Write Characteristics 6800 Mode ERD LCD Panel Used in Full Graphics Mode Design Examples LCD Panel Used in Character Mode Display Command Byte Display Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller Array Connector Numbering C D E F G H 140