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Xilinx ML561 manual Power Regulation, Power Distribution

Models: ML561

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R

Power Regulation

OFF

12V Input

Jack

HSTL

SPY

RLDRAM II

A1

FPGA3

					RS232
				7SEG1	Driver
QDRII				Serial Header
		VCCAUX /		Serial Header


		VCCO				RESET
		VCCO				RESET

5V Banana Jacks

ON

OFF

5V Input

Jack

12V -> 5V

3.3V

RLDRAM II

FPGA3 LEDs

	SPY	QDRII		HSTL
	SPY			VTT & VREF
	Test Header 3			VTT & VREF
	Test Header 3

JTAG Test Header

Config3

7SEG3 DIP3

System ACE

Controller

	Pwr Measure Header		LCD Connector				HSTL
	Pwr Measure Header		LCD Connector
				LCD

PROG	USB

JTAG

UG199_c3_08_050106

Figure 3-8:LCD Panel Connector for Possible LCD Support

The product specification at http://www.displaytech.com.hk/pdf/graphic/64128e%20series-v10.PDF provides more information. Appendix C, “LCD Interface,” describes the LCD operation in detail.

Power Regulation

This section describes the devices that supply power to the Virtex-5 FPGA ML561 Development Board. For electrical requirements and power consumption, see Chapter 4, “Electrical Requirements.”

Power Distribution

The ML561 board uses +5V to drive numerous voltage regulators. Figure 3-9shows a general overview of the power distribution system.

+5V										Board Power
										Board Power
	Slide									3.3V
	Slide									3.3V
	Switch									FPGA Power

+12V					12V -> 5V
+12V					12V -> 5V
	Slide									VCCINT or VCCAUX/VCCO
	Slide									VCCINT or VCCAUX/VCCO
	Switch									FPGA Power
										FPGA Power
										SSTL18, HSTL, or SSTL2
										Memory Power


										SSTL18, HSTL, or SSTL2
										SSTL18, HSTL, or SSTL2

MGT

Power

VTT

VREF

To Devices

MGT Power

To All FPGAs

To FPGAs

To Memories

VTT

VREF

UG199_c3_09_050106

Figure 3-9:Virtex-5 FPGA ML561 Development Board Power Distribution System

The Virtex-5 FPGA ML561 Development Board is powered through the +5V input jack (J28) from the power supply included in the ML561 Tool Kit. Alternatively, the +5V can

Virtex-5 FPGA ML561 User Guide

www.xilinx.com

33

UG199 (v1.2) April 19, 2008

Image 33

Xilinx ML561 manual Power Regulation, Power Distribution

Contents

UG199 v1.2 April 19 Virtex-5 Fpga ML561 Memory Interfaces Development BoardDate Version Revision Revision HistoryTable of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide Guide Contents About This GuideAdditional Documentation Preface About This Guide Additional Support ResourcesTerminology ConventionsTypographical Online DocumentVirtex-5 Fpga ML561 User Guide About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit IntroductionIntroduction Virtex-5 Fpga ML561 Memory Interfaces Development Board2Virtex-5 Fpga ML561 Development Board Virtex-5 Fpga ML561 Memory Interfaces Development BoardIntroduction Initial Board Check Before Applying Power Getting StartedDocumentation and Reference Design CD Getting Started Applying Power to the BoardHardware Overview Hardware DescriptionHardware Description 1ML561 XC5VLX50T-FFG1136 Board Placement DiagramMemories DDR400 Sdram ComponentsHardware Overview Rldram II Devices DDR2 Sdram ComponentsMemory Details DDR400 and DDR2 Component MemoriesMemory Details DDR2ODT10, DDR2RAS,CAS,WEN DDR1RAS,CAS,WEN, DDR1CKEDDR2 Sdram Dimm Dimm DDR2DIMMRAS,CAS,WE,RESETNDDR2DIMM15CNTLPAR DDR2DIMM15CNTLPARERRQdrii and Rldram II Memories QDR2R,W,DLLOFFN External Interfaces RS-232Clocks MHz Lvpecl Clock SMA ClockMHz Clock User I/Os DIP SwitchMHz System ACE Controller Oscillator GTP ClocksSeven-Segment Displays Seven-Segment Display Signal MappingLight Emitting Diodes LEDs PushbuttonsPower On or Off Slide Switch Power Measurement HeaderSoft Touch Probe Points Liquid Crystal Display Connector Power Regulation Power DistributionPower Regulation 10PTH05010 Voltage Regulator Voltage RegulatorsOutput Voltage 16Manual Voltage MarginingBoard Design Considerations 11ML561 Revision a PCB Stack-Up Board Design ConsiderationsTOP 19ML561 Revision a PCB Controlled ImpedanceElectrical Requirements Power ConsumptionPower Consumed DDR400 Component Interface Total Available PowerTotal Power Consumed CurrentPower Modules Capacity 2Power Planes Voltage Regulator Module VRM Part Electrical RequirementsStack-Up 3ML561 Power Plane Capacities Power ConsumptionCurrent Power Excess Device Description Quantity Power Consumed by Power PlaneElectrical Requirements 3ML561 Power Plane Capacities Power Consumption 3ML561 Power Plane Capacities Current Power Excess Device DescriptionTotal Power Consumed 53.2 Fpga Internal Power Budget 4ML561 Fpga Power Estimate SummaryFpga #21 Termination and Transmission Line Summaries Signal Integrity Recommendations2DDR2 Sdram Dimm Terminations Signal Fpga Driver HSTLI18 5RLDRAM II Terminations SignalHSTLIDCI18 HSTLIIDCI18Signal Integrity Recommendations Configuration Modes ConfigurationJtag Chain Configuration 1Configuration ModesJtag Port Parallel IV Cable PortSystem ACE Interface Configuration Introduction ML561 Hardware-Simulation CorrelationML561 Hardware-Simulation Correlation Test Setup1Single Trapezoid Eye Mask Definition Test Setup2Two Triangular Eye Mask Definitions for VIH and VIL Signal Integrity Correlation ResultsDDR2 Component Write Operation Signal Integrity Correlation Results2DDR2 Component Write Operation Correlation Results Measurement3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 DDR2 Component Read Operation Fpga SSTL18IIDCII5DDR2 Component Read Operation Correlation Results Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 DIMM, 75 Ω ODT DDR2 Dimm Write OperationNoise Margin Overshoot / Undershoot Measurement 8DIP12 Settings DescriptionUG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 10DDR2 Dimm Read Operation Correlation Results DVW % DDR2 Dimm Read OperationUG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 Qdrii Write Operation Fpga HSTLI1812 Qdrii Write Operation Correlation Results 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 Qdrii Read Operation Fpga HSTLIDCI1814QDRII Read Operation Correlation Results UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Summary and Recommendations Summary and RecommendationsNoise Margin Overshoot Operation 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis ModelML561 Hardware-Simulation Correlation Fpga #1 Pinout Fpga PinoutsTable A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA3TOFPGA1MIITXCLK FPGA2TOFPGA1MIITXCLKFPGA2TOFPGA1MIITXDATA0 FPGA3TOFPGA1MIITXDATA0Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMMDQBY0B4 DDR2DIMM3CK2PDDR2DIMM3CKE0 DDR2DIMMDQBY0B5DDR2DIMMDQBY7B7 DDR2DIMMDQBY4B4DDR2DIMMDQBY4B5 DDR2DIMMDQCB07B0DDR2DIMMDQBY11B5 DDR2DIMM5CS1N DDR2DIMM5CS0NDDR2DIMMDQBY11B6 DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal NameFPGA2SOFTTOUCHBY1B7 FPGA2DIP0FPGA2DIP1 FPGA2SPYHOLEBK15FPGA2TXN1BK120 FPGA2USBDSRN FPGA2TXN0BK120 FPGA2USBCTSNFPGA2TXP0BK120 FPGA2USBDTRN FPGA2TXP1BK120 FPGA2USBRSTNFpga #3 Pinout Table A-3FPGA #3 Pinout Signal Name Qdrii Memory InterfaceQDR2DBY4B1 QDR2DBY0B5QDR2DBY0B6 QDR2DBY4B2QDR2QBY3B2 QDR2DBY7B6QDR2DBY7B7 QDR2QBY3B3QDR2QBY7B4 QDR2QBY6B7QDR2QBY6B8 QDR2QBY7B5RLD2DBY0B7 RLD2DQBY0B1 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 RLD2DQBY0B3RLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6 FPGA3RESETNINCLKTOFPGA3MGTN EXTCLKTOFPGA3N CLKTOFPGA3MGTP EXTCLKTOFPGA3PTable A-3FPGA #3 Pinout Signal Name Table B-1Bill of Materials Bill of Materials4A LDO Appendix B Bill of Materials Table B-1Bill of MaterialsVirtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials LCD Interface GeneralDisplay Hardware Design Hardware Schematic Diagram Table C-1Display Controller Specifications ParameterAppendix C LCD Interface Peripheral Device KS0713 Hardware Schematic Diagram64128EFCBC-XLP Block Diagram Table C-2 LCD Panel Controller Operation124 Controller LCD Panel Connections Figure C-5Power Supply Circuits Controller Power Supply CircuitsFigure C-6LCD Controller Initialization Flow Operation Example of the 64128EFCBC-3LPOFF Table C-4Resistor Value Settings Table C-5 Reference Voltage ParametersReference Voltage Parameter α Table C-6Display Instructions Instruction SetSet page address Hardware Schematic Diagram Table C-6Display InstructionsEON Appendix C LCD Interface Table C-6Display InstructionsERD Read/Write Characteristics 6800 ModeDesign Examples LCD Panel Used in Full Graphics ModeDisplay Command Byte LCD Panel Used in Character ModeDisplay Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller C D E F G H Array Connector Numbering140