Xilinx ML561 manual 16Summary of Worst-Case SI Characteristics

Chapter 7: ML561 Hardware-Simulation Correlation

Table 7-16summarizes the extrapolated SI characteristics of all six test signals.

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Table 7-16:Summary of Worst-Case SI Characteristics

	ΔDVW	ΔISI	Noise Margin	Overshoot /
Operation				Undershoot Margin
	(% UI)	(% UI)	(% VREF)
				(% VREF)
DDR2 Component Write	1.27 ns	127 ps	570 mV	685 mV
	(84%)	(8.5%)	(63.3%)	(76.1%)
DDR2 Component Read	1.29 ns	178 ps	867 mV	349 mV
	(86%)	(11.9%)	(96.3%)	(38.9%)
DDR2 DIMM Write	1.23 ns	117 ps	253 mV	981 mV
	(82%)	(7.8%)	(28.1%)	(109.0%)
DDR2 DIMM Read	1.23 ns	224 ps	546 mV	989 mV
	(82%)	(14.9%)	(60.7%)	(109.9%)
QDRII Write	1.38 ns	313 ps	687 mV	186 mV
	(83%)	(18.8%)	(76.3%)	(20.7%)
QDRII Read	1.45 ns	85 ps	509 mV	1183 mV
	(87%)	(5.1%)	(56.5%)	(131.5%)

Here are some observations about extrapolated SI characteristics among these test signals:

•The Data Valid Window (DVW) values already account for the degradation caused by ISI due to the PRBS6 test pattern. For timing analysis, two values need to be taken into consideration appropriately. For a PRBS6 test pattern, the worst-case DVW value (after discounting for ISI) is 82% UI for DDR2 DIMM operations.

•DDR2 write operations, as compared to QDRII write operations, have a lower noise margin due to the always on nature of the DCI termination on the DQ signal for the SSTL18_II_DCI I/O standard at the FPGA. Consequently, the overshoot/undershoot margin for DDR2 write operations is higher than for QDRII write operations. The DDR2 DIMM write operation has the lowest VIL noise margin of 107 mV.

•For read operations, the sum of VIH and VIL noise margins beyond the AC value specifications is at least 509 mV (56.6% of VREF). QDRII read operations have the lowest VIL noise margin of 201 mV.

•All six signals have positive values for overshoot and undershoot margins. QDRII write operations have the lowest undershoot margin value of 30 mV.

(For Table 5-1, page 48 through Table 5-5, page 49, the recommendations remain the same except for a clarification for DDR2 ODT as “75 ohm ODT”.)

92	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008