Table B-1Bill of Materials | Xilinx ML561 manual

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Appendix B

Bill of Materials

This appendix lists the bill of materials (BOM) for many of the components used for the assembly of the Virtex-5 FPGA ML561 Development Board, Revision A. Wherever feasible and practical, the associated reference designators are also listed for each part. The component part number in the “Mfr. Part Number” column includes a link to the corresponding manufacturer or supplier’s web page. Check with the manufacturer for current information regarding the location and status of component data sheets.

Table B-1:Bill of Materials

	Category	Description	Manufacturer	Mfr. Part Number	Reference Designators

	FPGA	Virtex-5 FPGA	Xilinx	XC5VLX50T-FFG1136 -2 speed grade	U5, U7, U34

		DDR2 Registered DIMM	Micron	MT9HTF6472Y-667 (RDIMM)	XP1, XP2, XP3, XP4, XP5
		DDR2 Registered DIMM	Micron	MT9HTF6472Y-667 (RDIMM)	(DIMM)
					(DIMM)

		DDR2 Unbuffered DIMM	Micron	MT9HTF6472AY-667 (UDIMM)	XP1, XP2, XP3, XP4, XP5
		DDR2 Unbuffered DIMM	Micron	MT9HTF6472AY-667 (UDIMM)	(DIMM)
					(DIMM)

		DDR400 SDRAM	Micron	MT46V32M16BN-5B	U6, U9
	Memory
	Memory	DDR2 SDRAM	Micron	MT47H32M16CC-3	U11, U12
		DDR2 SDRAM	Micron	MT47H32M16CC-3	U11, U12

		QDRII	Samsung	K7R643684M-FC30	U35, U41

		RLDRAM II	Micron	MT49H16M18BM-25	U25, U33

		DIMM Socket	SMP Technology	B037-2401-010-0-Z	XP1, XP2, XP3, XP4, XP5
		DIMM Socket	SMP Technology	B037-2401-010-0-Z	(Socket)
					(Socket)

	Clock	33 MHz Oscillator	Epson	SG-8002CA-33.0000M-PCC	Y2, Y3

		200 MHz Oscillator	Epson	EG2121CA-200.0000M-PHPAB	Y1
		200 MHz Oscillator	Epson	EG2121CA-200.0000M-PHPAB	Y1

	Configuration	System ACE Controller	Xilinx	XCCACE-TQG144I	U45

		JTAG Port	Molex	87832-1420	P114
		JTAG Port	Molex	87832-1420	P114

Virtex-5 FPGA ML561 User Guide

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UG199 (v1.2) April 19, 2008

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Xilinx ML561 manual Table B-1Bill of Materials

Contents

UG199 v1.2 April 19 Virtex-5 Fpga ML561 Memory Interfaces Development Board Date Version Revision Revision History Table of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide About This Guide Guide ContentsAdditional Documentation Preface About This Guide Additional Support Resources Online Document ConventionsTerminology Typographical Virtex-5 Fpga ML561 User Guide About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit Introduction Introduction Virtex-5 Fpga ML561 Memory Interfaces Development Board 2Virtex-5 Fpga ML561 Development Board Virtex-5 Fpga ML561 Memory Interfaces Development Board Introduction Getting Started Initial Board Check Before Applying PowerDocumentation and Reference Design CD Getting Started Applying Power to the Board Hardware Overview Hardware Description Hardware Description 1ML561 XC5VLX50T-FFG1136 Board Placement Diagram DDR400 Sdram Components MemoriesHardware Overview Rldram II Devices DDR2 Sdram Components DDR400 and DDR2 Component Memories Memory DetailsMemory Details DDR2ODT10, DDR2RAS,CAS,WEN DDR1RAS,CAS,WEN, DDR1CKE DDR2 Sdram Dimm DDR2DIMM15CNTLPARERR DDR2DIMMRAS,CAS,WE,RESETNDimm DDR2DIMM15CNTLPAR Qdrii and Rldram II Memories QDR2R,W,DLLOFFN RS-232 External InterfacesClocks SMA Clock MHz Lvpecl ClockMHz Clock GTP Clocks DIP SwitchUser I/Os MHz System ACE Controller Oscillator Pushbuttons Seven-Segment Display Signal MappingSeven-Segment Displays Light Emitting Diodes LEDs Power Measurement Header Power On or Off Slide SwitchSoft Touch Probe Points Liquid Crystal Display Connector Power Distribution Power RegulationPower Regulation 10PTH05010 Voltage Regulator Voltage Regulators Output Voltage 16Manual Voltage Margining Board Design Considerations 11ML561 Revision a PCB Stack-Up Board Design Considerations TOP 19ML561 Revision a PCB Controlled Impedance Electrical Requirements Power Consumption Current Total Available PowerPower Consumed DDR400 Component Interface Total Power Consumed Power Modules Capacity Electrical Requirements 2Power Planes Voltage Regulator Module VRM PartStack-Up Power Consumed by Power Plane Power Consumption3ML561 Power Plane Capacities Current Power Excess Device Description Quantity Electrical Requirements 3ML561 Power Plane Capacities Current Power Excess Device Description Power Consumption 3ML561 Power Plane CapacitiesTotal Power Consumed 53.2 4ML561 Fpga Power Estimate Summary Fpga Internal Power BudgetFpga #21 Termination and Transmission Line Summaries Signal Integrity Recommendations 2DDR2 Sdram Dimm Terminations Signal Fpga Driver HSTLIIDCI18 5RLDRAM II Terminations SignalHSTLI18 HSTLIDCI18 Signal Integrity Recommendations Configuration Modes Configuration Parallel IV Cable Port Configuration 1Configuration ModesJtag Chain Jtag Port System ACE Interface Configuration Introduction ML561 Hardware-Simulation Correlation ML561 Hardware-Simulation Correlation Test Setup 1Single Trapezoid Eye Mask Definition Test Setup 2Two Triangular Eye Mask Definitions for VIH and VIL Signal Integrity Correlation Results Measurement Signal Integrity Correlation ResultsDDR2 Component Write Operation 2DDR2 Component Write Operation Correlation Results 3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 Fpga SSTL18IIDCII DDR2 Component Read Operation5DDR2 Component Read Operation Correlation Results Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 DIMM, 75 Ω ODT DDR2 Dimm Write Operation Noise Margin Overshoot / Undershoot Measurement 8DIP12 Settings Description UG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 10DDR2 Dimm Read Operation Correlation Results DVW % DDR2 Dimm Read Operation UG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 Fpga HSTLI18 Qdrii Write Operation12 Qdrii Write Operation Correlation Results 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 Fpga HSTLIDCI18 Qdrii Read Operation14QDRII Read Operation Correlation Results UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Summary and Recommendations Summary and RecommendationsNoise Margin Overshoot Operation 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis Model ML561 Hardware-Simulation Correlation Fpga #1 Pinout Fpga Pinouts Table A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA3TOFPGA1MIITXDATA0 FPGA2TOFPGA1MIITXCLKFPGA3TOFPGA1MIITXCLK FPGA2TOFPGA1MIITXDATA0 Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMMDQBY0B5 DDR2DIMM3CK2PDDR2DIMMDQBY0B4 DDR2DIMM3CKE0 DDR2DIMMDQCB07B0 DDR2DIMMDQBY4B4DDR2DIMMDQBY7B7 DDR2DIMMDQBY4B5 DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7 DDR2DIMM5CS0NDDR2DIMMDQBY11B5 DDR2DIMM5CS1N DDR2DIMMDQBY11B6 Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name FPGA2SPYHOLEBK15 FPGA2DIP0FPGA2SOFTTOUCHBY1B7 FPGA2DIP1 FPGA2TXP1BK120 FPGA2USBRSTN FPGA2TXN0BK120 FPGA2USBCTSNFPGA2TXN1BK120 FPGA2USBDSRN FPGA2TXP0BK120 FPGA2USBDTRN Fpga #3 Pinout Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface QDR2DBY4B2 QDR2DBY0B5QDR2DBY4B1 QDR2DBY0B6 QDR2QBY3B3 QDR2DBY7B6QDR2QBY3B2 QDR2DBY7B7 QDR2QBY7B5 QDR2QBY6B7QDR2QBY7B4 QDR2QBY6B8 RLD2DQBY0B3 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0RLD2DBY0B7 RLD2DQBY0B1 RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 CLKTOFPGA3MGTP EXTCLKTOFPGA3P FPGA3RESETNINRLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6 CLKTOFPGA3MGTN EXTCLKTOFPGA3N Table A-3FPGA #3 Pinout Signal Name Table B-1Bill of Materials Bill of Materials 4A LDO Appendix B Bill of Materials Table B-1Bill of Materials Virtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials General LCD InterfaceDisplay Hardware Design Table C-1Display Controller Specifications Parameter Hardware Schematic DiagramAppendix C LCD Interface Peripheral Device KS0713 Hardware Schematic Diagram 64128EFCBC-XLP Block Diagram Table C-2 LCD Panel Controller Operation 124 Controller LCD Panel Connections Figure C-5Power Supply Circuits Controller Power Supply Circuits Figure C-6LCD Controller Initialization Flow Operation Example of the 64128EFCBC-3LP OFF Table C-5 Reference Voltage Parameters Table C-4Resistor Value SettingsReference Voltage Parameter α Table C-6Display Instructions Instruction Set Set page address Hardware Schematic Diagram Table C-6Display Instructions EON Appendix C LCD Interface Table C-6Display Instructions ERD Read/Write Characteristics 6800 Mode Design Examples LCD Panel Used in Full Graphics Mode Display Command Byte LCD Panel Used in Character Mode Display Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller C D E F G H Array Connector Numbering 140