Xilinx ML561 manual Summary and Recommendations, Noise Margin Overshoot Operation

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Summary and Recommendations

Summary and Recommendations

The first objective of this exercise is to establish correlation between hardware measurements and the simulation at the probe point. The intention was to validate the simulation model for the targeted signal. The degree of correlation achieved is looked at in terms of absolute difference as well as relative percentage. The relative percentage differences are presented in terms of unit interval (UI) for timing characteristics and in terms of VREF voltage for the voltage margin characteristics.

Correlation simulation is performed under ideal conditions, that is, the stimulus is generated without any jitter. On the other hand, the hardware measurements are subject to jitter (which tends to increase ISI), board-level power fluctuation (which can affect the eye amplitude), and stability of the probing station. Thus some correlation differences are expected. The user ultimately uses his or her own judgment to account for these differences, and adjusts the values extrapolated for quality of signal at the receiver IOB.

Table 7-15contains this information for all six test signals.

Table 7-15:Summary of Correlation Differences: Hardware vs. Simulation

	ΔDVW	ΔISI	Noise Margin	Overshoot /
Operation				Undershoot Margin
	(% UI(1))	(% UI)	(% VREF)
				(% VREF)
DDR2 Component Write	40 ps	47 ps	98 mV	69 mV
	(2.6%)	(3.2%)	(10.9%)	(7.6%)
DDR2 Component Read	0 ps	43 ps	6 mV	244 mV
	(0%)	(2.9%)	(0.7%)	(17.2%)
DDR2 DIMM Write	218 ps	366 ps	112 mV	2 mV
	(14.5%)	(24.5%)	(12.6%)	(0.3%)
DDR2 DIMM Read	39 ps	44 ps	90 mV	208 mV
	(2.6%)	(2.9%)	(10.0%)	(23.1%)
QDRII Write	10 ps	107 ps	2 mV	85 mV
	(0.6%)	(6.4%)	(0.3%)	(9.4%)
QDRII Read	106 ps	27 ps	386 mV	50 mV
	(6.4%)	(1.6%)	(31.8%)	(5.6%)

Notes:

1. Unit Interval (UI): 1.5 ns for DDR2 and 1.67 ns for QDRII. VREF = 0.9V for DDR2 and QDRII.

There are varying degrees of correlation differences among the six test signals. In general, there is a good match between hardware measurements and the correlation simulation, except for some yet-to-be analyzed differences, for example, DDR2 DIMM Write DVW and QDRII read noise margin.

The remainder of this section summarizes the extrapolation results of the data bit interface for all six memory operations on the ML561 board. The measure of SI characteristics of each signal is determined by the worst-case extrapolation measurement from among the simulations with drivers at slow-weak and fast-strong corners. The values chosen between these two corner cases are:

•Minimum of DVW, noise margin, and overshoot/undershoot margin

•Maximum of ISI

Virtex-5 FPGA ML561 User Guide www.xilinx.com 91

UG199 (v1.2) April 19, 2008