QDR2DBY7B6, QDR2QBY3B2, QDR2DBY7B7, QDR2QBY3B3 | Xilinx ML561

Appendix A: FPGA Pinouts

Table A-3:FPGA #3 Pinout (Continued)

R

Signal Name	Pin		Signal Name	Pin

	QDRII Memory Interface (cont.)

QDR2_D_BY7_B6	U28		QDR2_Q_BY3_B2	G27

QDR2_D_BY7_B7	U27		QDR2_Q_BY3_B3	F26

QDR2_D_BY7_B8	T29		QDR2_Q_BY3_B4	F25

QDR2_Q_BY0_B0	J34		QDR2_Q_BY3_B5	H24

QDR2_Q_BY0_B1	H34		QDR2_Q_BY3_B6	H25

QDR2_Q_BY0_B2	H33		QDR2_Q_BY3_B7	G26

QDR2_Q_BY0_B3	J32		QDR2_Q_BY3_B8	G25

QDR2_Q_BY0_B4	F34		QDR2_Q_BY4_B0	AP32

QDR2_Q_BY0_B5	G33		QDR2_Q_BY4_B1	AN32

QDR2_Q_BY0_B6	E33		QDR2_Q_BY4_B2	AN33

QDR2_Q_BY0_B7	E32		QDR2_Q_BY4_B3	AN34

QDR2_Q_BY0_B8	E34		QDR2_Q_BY4_B4	AM32

QDR2_Q_BY1_B0	T24		QDR2_Q_BY4_B5	AM33

QDR2_Q_BY1_B1	R24		QDR2_Q_BY4_B6	AL33

QDR2_Q_BY1_B2	N25		QDR2_Q_BY4_B7	AL34

QDR2_Q_BY1_B3	P25		QDR2_Q_BY4_B8	AK32

QDR2_Q_BY1_B4	P24		QDR2_Q_BY5_B0	AF34

QDR2_Q_BY1_B5	N24		QDR2_Q_BY5_B1	AE33

QDR2_Q_BY1_B6	P27		QDR2_Q_BY5_B2	AF33

QDR2_Q_BY1_B7	P26		QDR2_Q_BY5_B3	AB33

QDR2_Q_BY1_B8	N28		QDR2_Q_BY5_B4	AC33

QDR2_Q_BY2_B0	G32		QDR2_Q_BY5_B5	AB32

QDR2_Q_BY2_B1	D34		QDR2_Q_BY5_B6	AC32

QDR2_Q_BY2_B2	C34		QDR2_Q_BY5_B7	AD34

QDR2_Q_BY2_B3	D32		QDR2_Q_BY5_B8	AC34

QDR2_Q_BY2_B4	C32		QDR2_Q_BY6_B0	Y32

QDR2_Q_BY2_B5	C33		QDR2_Q_BY6_B1	Y34

QDR2_Q_BY2_B6	B33		QDR2_Q_BY6_B2	AA34

QDR2_Q_BY2_B7	A33		QDR2_Q_BY6_B3	AA33

QDR2_Q_BY2_B8	B32		QDR2_Q_BY6_B4	Y33

QDR2_Q_BY3_B0	H28		QDR2_Q_BY6_B5	V34

QDR2_Q_BY3_B1	H27		QDR2_Q_BY6_B6	W34

110	www.xilinx.com	Virtex-5 FPGA ML561 User Guide
		UG199 (v1.2) April 19, 2008

Image 110

Xilinx ML561 QDR2DBY7B6, QDR2QBY3B2, QDR2DBY7B7, QDR2QBY3B3, QDR2DBY7B8, QDR2QBY3B4, QDR2QBY0B0, QDR2QBY3B5, QDR2QBY0B1

Contents

Virtex-5 Fpga ML561 Memory Interfaces Development Board UG199 v1.2 April 19 Revision History Date Version Revision Table of Contents Electrical Requirements Appendix B Bill of Materials Appendix C LCD Interface Virtex-5 Fpga ML561 User Guide Additional Documentation Guide ContentsAbout This Guide Additional Support Resources Preface About This Guide Typographical ConventionsTerminology Online Document Virtex-5 Fpga ML561 User Guide Introduction About the Virtex-5 Fpga ML561 Memory Interfaces Tool Kit Virtex-5 Fpga ML561 Memory Interfaces Development Board Introduction Virtex-5 Fpga ML561 Memory Interfaces Development Board 2Virtex-5 Fpga ML561 Development Board Introduction Documentation and Reference Design CD Initial Board Check Before Applying PowerGetting Started Applying Power to the Board Getting Started Hardware Description Hardware Overview 1ML561 XC5VLX50T-FFG1136 Board Placement Diagram Hardware Description Hardware Overview MemoriesDDR400 Sdram Components DDR2 Sdram Components Rldram II Devices Memory Details Memory DetailsDDR400 and DDR2 Component Memories DDR1RAS,CAS,WEN, DDR1CKE DDR2ODT10, DDR2RAS,CAS,WEN DDR2 Sdram Dimm DDR2DIMM15CNTLPAR DDR2DIMMRAS,CAS,WE,RESETNDimm DDR2DIMM15CNTLPARERR Qdrii and Rldram II Memories QDR2R,W,DLLOFFN Clocks External InterfacesRS-232 MHz Clock MHz Lvpecl ClockSMA Clock MHz System ACE Controller Oscillator DIP SwitchUser I/Os GTP Clocks Light Emitting Diodes LEDs Seven-Segment Display Signal MappingSeven-Segment Displays Pushbuttons Soft Touch Probe Points Power On or Off Slide SwitchPower Measurement Header Liquid Crystal Display Connector Power Regulation Power RegulationPower Distribution Voltage Regulators 10PTH05010 Voltage Regulator 16Manual Voltage Margining Output Voltage Board Design Considerations Board Design Considerations 11ML561 Revision a PCB Stack-Up 19ML561 Revision a PCB Controlled Impedance TOP Power Consumption Electrical Requirements Total Power Consumed Total Available PowerPower Consumed DDR400 Component Interface Current Power Modules Capacity Stack-Up 2Power Planes Voltage Regulator Module VRM PartElectrical Requirements Current Power Excess Device Description Quantity Power Consumption3ML561 Power Plane Capacities Power Consumed by Power Plane Electrical Requirements 3ML561 Power Plane Capacities Total Power Consumed 53.2 Power Consumption 3ML561 Power Plane CapacitiesCurrent Power Excess Device Description Fpga #21 Fpga Internal Power Budget4ML561 Fpga Power Estimate Summary Signal Integrity Recommendations Termination and Transmission Line Summaries 2DDR2 Sdram Dimm Terminations Signal Fpga Driver HSTLIDCI18 5RLDRAM II Terminations SignalHSTLI18 HSTLIIDCI18 Signal Integrity Recommendations Configuration Configuration Modes Jtag Port Configuration 1Configuration ModesJtag Chain Parallel IV Cable Port System ACE Interface Configuration ML561 Hardware-Simulation Correlation Introduction Test Setup ML561 Hardware-Simulation Correlation Test Setup 1Single Trapezoid Eye Mask Definition Signal Integrity Correlation Results 2Two Triangular Eye Mask Definitions for VIH and VIL 2DDR2 Component Write Operation Correlation Results Signal Integrity Correlation ResultsDDR2 Component Write Operation Measurement 3DIP12 Settings Description Voltage mV Voltage mV Time ns UG199c711071007 5DDR2 Component Read Operation Correlation Results DDR2 Component Read OperationFpga SSTL18IIDCII Time ns UG199c715071107 UG199c717071007 UG199c719071007 DDR2 Dimm Write Operation DDR2 DIMM, 75 Ω ODT 8DIP12 Settings Description Noise Margin Overshoot / Undershoot Measurement UG199c722071107 UG199c724071107 UG199c726071007 UG199c729071007 DDR2 Dimm Read Operation 10DDR2 Dimm Read Operation Correlation Results DVW % UG199c731071107 1800.0 1600.0 1400.0 1200.0 1000.0 UG199c735071007 UG199c737071007 12 Qdrii Write Operation Correlation Results Qdrii Write OperationFpga HSTLI18 800.0 600.0 400.0 200.0 000 Probe 3C7.1 at pin 1200.0 1600.0 UG199c742071107 UG199c744070907 3100.0 2600.0 2100.0 1600.0 1100.0 14QDRII Read Operation Correlation Results Qdrii Read OperationFpga HSTLIDCI18 UG199c749071107 1900.0 1700.0 1500.0 1300.0 1100.0 UG199c753070907 UG199c755070907 Noise Margin Overshoot Operation Summary and RecommendationsSummary and Recommendations 16Summary of Worst-Case SI Characteristics How to Generate a User-Specific Fpga Ibis Model How to Generate a User-Specific Fpga Ibis Model ML561 Hardware-Simulation Correlation Fpga Pinouts Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #1 Clock and Reset Signals FPGA2TOFPGA1MIITXDATA0 FPGA2TOFPGA1MIITXCLKFPGA3TOFPGA1MIITXCLK FPGA3TOFPGA1MIITXDATA0 Fpga #1 Pinout Table A-1FPGA #1 Pinout Signal Name Fpga #2 Pinout DDR2DIMM3CKE0 DDR2DIMM3CK2PDDR2DIMMDQBY0B4 DDR2DIMMDQBY0B5 DDR2DIMMDQBY4B5 DDR2DIMMDQBY4B4DDR2DIMMDQBY7B7 DDR2DIMMDQCB07B0 DDR2DIMMDQBY11B6 DDR2DIMM5CS0NDDR2DIMMDQBY11B5 DDR2DIMM5CS1N DDR2DIMM5ODT0 AA9 DDR2DIMMDQBY11B7 Table A-2FPGA #2 Pinout Signal Name Fpga #2 Pinout Table A-2FPGA #2 Pinout Signal Name Fpga #2 Clock and Reset Signals FPGA2DIP1 FPGA2DIP0FPGA2SOFTTOUCHBY1B7 FPGA2SPYHOLEBK15 FPGA2TXP0BK120 FPGA2USBDTRN FPGA2TXN0BK120 FPGA2USBCTSNFPGA2TXN1BK120 FPGA2USBDSRN FPGA2TXP1BK120 FPGA2USBRSTN Table A-3FPGA #3 Pinout Signal Name Qdrii Memory Interface Fpga #3 Pinout QDR2DBY0B6 QDR2DBY0B5QDR2DBY4B1 QDR2DBY4B2 QDR2DBY7B7 QDR2DBY7B6QDR2QBY3B2 QDR2QBY3B3 QDR2QBY6B8 QDR2QBY6B7QDR2QBY7B4 QDR2QBY7B5 RLD2DBY0B8 RLD2DQBY0B2 RLD2DBY1B0 RLD2DBY0B5 RLD2DMBY23N RLD2DBY0B6 RLD2DQBY0B0RLD2DBY0B7 RLD2DQBY0B1 RLD2DQBY0B3 CLKTOFPGA3MGTN EXTCLKTOFPGA3N FPGA3RESETNINRLD2DQBY3B4 RLD2DQBY3B7 RLD2DQBY3B5 RLD2DQBY3B8 RLD2DQBY3B6 CLKTOFPGA3MGTP EXTCLKTOFPGA3P Table A-3FPGA #3 Pinout Signal Name Bill of Materials Table B-1Bill of Materials Appendix B Bill of Materials Table B-1Bill of Materials 4A LDO Virtex-5 Fpga ML561 User Guide 117 Appendix B Bill of Materials Display Hardware Design LCD InterfaceGeneral Appendix C LCD Interface Hardware Schematic DiagramTable C-1Display Controller Specifications Parameter Hardware Schematic Diagram Peripheral Device KS0713 64128EFCBC-XLP Block Diagram Controller Operation Table C-2 LCD Panel 124 Controller LCD Panel Connections Controller Power Supply Circuits Figure C-5Power Supply Circuits Operation Example of the 64128EFCBC-3LP Figure C-6LCD Controller Initialization Flow OFF Reference Voltage Parameter α Table C-4Resistor Value SettingsTable C-5 Reference Voltage Parameters Instruction Set Table C-6Display Instructions Hardware Schematic Diagram Table C-6Display Instructions Set page address Appendix C LCD Interface Table C-6Display Instructions EON Read/Write Characteristics 6800 Mode ERD LCD Panel Used in Full Graphics Mode Design Examples LCD Panel Used in Character Mode Display Command Byte Display Data Byte Figure C-10Block RAM Organization Figure C-11LCD Character Generator Controller Array Connector Numbering C D E F G H 140