Freescale Semiconductor MC68HC908MR16 manuals
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Freescale Semiconductor MC68HC908MR16 Manual
282 pages 1.84 Mb
4 Revision History5 List of Chapters7 Table of Contents17 Chapter 1 General Description25 Chapter 2 Memory2.1 Introduction 2.2 Unimplemented Memory Locations 2.3 Reserved Memory Locations 26 2.4 I/O Section2.5 Memory Map27 Figure 2-1. MC68HC908MR32 Memory Map28 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 8)29 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 2 of 8)30 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 8)31 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 4 of 8)32 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 5 of 8)33 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 8)34 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 8)35 Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 8)36 Table 2-1 is a list of vector locations. Table 2-1. Vector Addresses 37 2.6 Monitor ROM2.7 Random-Access Memory (RAM) 38 2.8 FLASH Memory (FLASH)45 Chapter 3 Analog-to-Digital Converter (ADC)3.1 Introduction 3.2 Features 3.3 Functional Description 50 3.4 Interrupts3.5 Wait Mode 3.6 I/O Signals3.6.1 ADC Analog Power Pin (VDDAD) 3.6.2 ADC Analog Ground Pin (VSSAD) 3.6.3 ADC Voltage Reference Pin (VREFH) 3.6.4 ADC Voltage Reference Low Pin (VREFL) 3.6.5 ADC Voltage In (ADVIN) 3.6.6 ADC External Connections 51 3.7 I/O Registers57 Chapter 4 Clock Generator Module (CGM)4.1 Introduction 4.2 Features 4.3 Functional Description 64 4.4 I/O Signals4.4.1 Crystal Amplifier Input Pin (OSC1) 4.4.2 Crystal Amplifier Output Pin (OSC2) 4.4.3 External Filter Capacitor Pin (CGMXFC) 4.4.4 PLL Analog Power Pin (VDDA) 4.4.5 Oscillator Enable Signal (SIMOSCEN) 4.4.6 Crystal Output Frequency Signal (CGMXCLK) 4.4.7 CGM Base Clock Output (CGMOUT) 4.4.8 CGM CPU Interrupt (CGMINT) 65 4.5 CGM Registers69 4.6 Interrupts4.7 Wait Mode 70 4.8 Acquisition/Lock Time Specifications73 Chapter 5 Configuration Register (CONFIG)75 Chapter 6 Computer Operating Properly (COP)6.1 Introduction 6.2 Functional Description 76 6.3 I/O Signals6.3.1 CGMXCLK 6.3.2 COPCTL Write 6.3.3 Power-On Reset 6.3.4 Internal Reset 6.3.5 Reset Vector Fetch 79 Chapter 7 Central Processor Unit (CPU)91 Chapter 8 External Interrupt (IRQ)8.1 IntroductionFigure 8-2. IRQ I/O Register Summary 8.2 FeaturesFeatures of the IRQ module include: A dedicated external interrupt pin, IRQ Hysteresis buffers 8.3 Functional DescriptionFigure 8-1. IRQ Module Block Diagram 92 8.4 IRQ Pin94 8.5 IRQ Status and Control Register97 Chapter 9 Low-Voltage Inhibit (LVI)101 Chapter 10 Input/Output (I/O) Ports (PORTS)113 Chapter 11 Power-On Reset (POR)11.1 Introduction 11.2 Functional Description 115 Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC)157 Chapter 13 Serial Communications Interface Module (SCI)181 Chapter 14 System Integration Module (SIM)195 Chapter 15 Serial Peripheral Interface Module (SPI)215 Chapter 16 Timer Interface A (TIMA)235 Chapter 17 Timer Interface B (TIMB)17.1 Introduction 17.2 Features 17.3 Functional Description 243 17.4 Interrupts17.5 Wait Mode 17.6 I/O Signals17.6.1 TIMB Clock Pin (PTE0/TCLKB) 17.6.2 TIMB Channel I/O Pins (PTE1/TCH0BPTE2/TCH1B) 244 17.7 I/O Registers251 Chapter 18 Development Support265 Chapter 19 Electrical Specifications275 Chapter 20 Ordering Information and Mechanical Specifications20.1 Introduction 20.2 Order Numbers
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