Instruction set
Note: For instruction names, the case does not matter. Register names are:
R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13 (or SP), R14 (or LP or LR) and R15 (or PC). Setting the S flag on an instruction causes the instruction to modify the flags.
Every instruction is evaluated ONLY if the attached condition is true. By default, the instruction is always evaluated. Separation between arguments can be either ‘,’ or spaces.
In the following examples, cond can be any of:
EQ | NE | CS | CC | MI | PL | VS | VC | HI | LS | GE | LT | GT | LE |
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| HS | LO |
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Equal | equal Not | set, Carry unsigned >= | clear Carry < | Negative | 0 or Positive | Overflow | No overflow | > Unsigned | Unsigned <= | >= | <= | > | <= |
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And Oprnd can be of the form:
Description | Form |
Immediate value | Cte |
| Note: cte is encoded on 8 bits + a rotation right encoded |
| on 4 bits. This means that not every value is possible. |
Logical shift left | Rm LSL Cte |
| Rm < Cte |
Logical shift right | Rm LSR Cte |
| Rm > Cte |
Arithmetic shift right | Rm ASR Cte |
| Rm >> Cte |
Rotate right | Rm ROR Cte |
| Rm >>> Cte |
Register | Rm |
Logical shift left | Rm LSL Rs |
| Rm < Rs |
Logical shift right | Rm LSR Rs |
| Rm > Rs |
Arithmetic shift right | Rm ASR Rs |
| Rm >> Rs |
Rotate right | Rm ROR Rs |
| Rm >>> Rs |
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