Saturn ASM mode

This section is only applicable to the Saturn ASM mode.

CPU architecture

This section’s purpose is to make experienced ASM programmers familiar with the Saturn architecture, not to teach anyone to program in Saturn ASM.

The Saturn CPU has 12 main registers:

A, B, C, D, R0, R1, R2, R3 and R4 are 64 bits register (see description below),

D0 and D1 are 20 bits pointers (you can only access memory through them, the Saturn is a little endian), PC, 20 bit program counter.

In addition, there are 16 flags ST0 to ST15 (12-15 being reserved for the system) that are 1 bit registers that are accessible separately, a carry that is set when operation overflow or tests are validated and can be tested using the GOC (Go On Carry) and GONC (Go On No Carry) jump instruction, a decimal/hexadecimal mode (SETHEX and SETDEC) that affects the way + and – instructions on the A, B, C and D register works (default Is HEX), and a 8 level return stack for GOSUBs (and RTN).

64 bit registers

Most operations on 64 bit registers will act on a specific “field”. A field is a division in a 64 bit register. If this represents the 16 nibbles of a 64 bit register, the fields cover the register as follows:

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WP

 

 

 

 

 

S

 

M

 

 

XS

B

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

The P field location depends of the value of the 4 bit P register (i.e. you can move it), and so does the WP field. Please look at the instruction set to see what instructions are available to the programmer. We will usually write “Rf” to indicate a register (uppercase) and a field (lowercase), as in Am.

In addition, in the new simulated Saturn architecture, 7 new fields F1 to F7 have been introduced. You can define the field mask by using the SETFLDn where n is a number between 1 and 7 to define the field Fn using the mask in Cw as in this example:

LC FF000000000000FF SETFLD1

LA 123456789ABCDEF0

LC 0FEDCBA987654321

A=A!C.F1

A is now equal to:

1F3456789ABCDEF1

ie: the instruction on F fields equate to:

reg1= (reg1 & ~ mask) ((reg1 & mask) operation (reg2 & mask))

These new fields are available for all instructions that previously used the so called ‘f’ encoding and includes the following instructions:

Reg=Reg&Reg.f, Reg=Reg!Reg.f, DATx=Reg.f, Reg=DATx.f, Reg=Reg+Cte.f, Reg=Reg-Cte.f, RegSRB.f, RReg=Reg.f, Reg=RReg.f and RegRRegEX.f.

The Development Library 6-19