2332 | REG C; | |
2340 | REG D; | |
2348 | REG R0; | |
2356 | REG R1; | |
2364 | REG R2; | |
2372 | REG R3; | |
2380 | REG R4; | |
2388 | U32 D0 | |
2392 | U32 | D1; |
2396 | U32 | P, P4, P4_32; // P4 = 4*P, P4_32 = |
2408 | U32 | ST; |
2412 | U32 HST; | |
2416 | U32 carry; // 0 or !0 | |
3420 | BOOL dec; // 0→hex or 1→dec | |
| U32 RSTK[NB_RSTK]; | |
| U32 | RSTK_i; // Index for next push. |
| REG FIELD[32]; // Field masks. | |
| U32 | FIELD_START[32]; // Lowest nibble of the field. |
| U32 | FIELD_LENGTH[32]; // Length of the field. |
Therefore, LDR R2 [R1 2316] allows you to read the lower 32 bits of the Saturn register A.
LDR R2 [R1 1]
LDR R3 [R2 1]
allows you to read the first 8 nibbles at Saturn address 01008
The following file can be used to declare your Saturn chipset structure.
"!ASM
CP=0
DCCP #1028 SREAD DCCP #1028 SWRITE DCCP #260 SPRIORITY DCCP 8 SRA
DCCP 8 SRB
DCCP 8 SRC
DCCP 8 SRD
DCCP 8 SR0
DCCP 8 SR1
DCCP 8 SR2
DCCP 8 SR3
DCCP 8 SR4
DCCP 4 SD0
DCCP 4 SD1
DCCP 4 SRP
DCCP 4 SRP4
DCCP 4 SRP32
DCCP 4 SST
DCCP 4 SHST DCCP 4 SCARRY DCCP 4 SDEC DCCP #32 SRSCK DCCP 4 SRSTKP DCCP #256 SFMASK DCCP #128 SFSTART DCCP #128 SFLENGTH @"