HP E1429A manual Pulse Register, Channel ID Register, Data Register

The high-speed internal (data) bus routes data between the A/D, digitizer memory, the local bus, and the VME (VXI data transfer) bus (Figure 3-7). There is no user-access to the high-speed internal bus.

The Pulse Register base +0816

The pulse register is a read/write register that generates high-speed clock signals when the traffic register’s high-speed clock source is set to ’pulse register’ .

Address

base + 0816

7 6 5 4 3 2 1 0

register read/write: generates high-speed bus clock pulse

Reading, or writing to this register generates a clock pulse for the internal high-speed bus.

The Channel ID Register base +0A16

The channel ID register is a read/write register that allows user-defined identifiers to be appended to each channel’s readings.

Address

base + 0A16

7	6	5	4	3	2	1	0
LSB	channel 1 ID		MSB	LSB	channel 2 ID		MSB

The ID assigned is represented by the 4 least significant bits of each reading. The ID bits are not stored in memory with the readings, but are appended to each reading as it is read over the VME (VXI data transfer) bus or Local bus.

The Data Register base +0C16

The data register is a read/write register used to retrieve readings from digitizer memory or to retrieve them from the digitizer’s A/D converter.

Address

base + 0C16

7 6 5 4 3 2 1 0

register read/write: retrieves a reading from digitizer memory

Each digitizer reading is stored in memory as a 12-bit, two’s complement number. When a reading is retrieved, it is expanded to 16-bits with the reading left-justified in the 16-bit field. The four least significant bits are normally zeros, but can be set as indicated by the channel ID register (base +0A16). The channel from which readings are retrieved is set with the "Data register Mode" field of the traffic register (base +0216).

364 Register Programming Appendix C