Bit Descriptions Sample/Hold: Setting bit 7 to ’1’ sets sample trigger hold which prevents the digitizer from accepting sample trigger signals.

Sample Infinite: Setting bit 6 to ’1’ sets infinite sample triggers. Triggering continues until aborted (base + 4116) or until the bit is set to ’0’ and the post arm reading count is reached. One sample trigger occurs after the bit is set to ’0’ even if the pos t-arm trigger count is reached. Sample Infinite overrides Sample Once (bit 5).

Sample Once: Setting bit 5 to ’1’ causes the digitizer to take one sample and return to the idle state, regardless of the pre-arm and post-arm reading counts. This bit should not be set if the pre-arm and post-arm reading mode is set (arm control register bit 3: base + 4B16 ). The bit is overridden by bit 6 (Sample Infinite).

Trigger Source: Bits 4 - 2 set the digitizer trigger (sample) source. Setting bits 4 - 2 as follows sets the trigger source indicated.

0 0 0 - reference oscillator output.

0 0 1 - ECLTrg0 trigger line.

0 1 0 - "Ext 1" BNC connector.

0 1 1 - internal TTL source as specified by bits 1 - 0. 1 0 0 - reference period / n.

1 0 1 - ECLTrg1 trigger line.

1 1 0 - "Ext 2" BNC connector.

1 1 1 - not used.

Internal TTL Sources: Bits 1 - 0 are additional sample sources which are selected when bits 4 - 2 are set to 011. The sources set by bits 1 - 0 are:

0 0 - VME (VXI data transfer) bus. Trigger when data register (base + 1216) is read.

0 1 - HP-IB Group Execute Trigger or IEEE-488.2 *TRG command 1 0 - TTLTrg trigger line

1 1 - user during local bus data transfer (does not take data)

358 Register Programming

Appendix C

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HP E1429A manual Register Programming Appendix C