Samsung S3F80JB manual T2CON Timer 2 Control Register E8H Set1 Bank1

S3F80JBCONTROL REGISTERS

T2CON — Timer 2 Control Register E8H Set1 Bank1

Bit Identifier

Reset Value

Read/Write

Addressing Mode

.7 and .6

.7	.6	.5	.4	.3	.2	.1	.0
0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Register addressing mode only

Timer 2 Input Clock Selection Bits

00 fOSC/4

01 fOSC/8

10 fOSC/16

1 1 Internal clock (counter A flip-flop, T-FF)

.5 and .4	Timer 2 Operating Mode Selection Bits
	0	0	Interval timer mode (counter cleared by match signal)
	0	1	Capture mode (rising edges, counter running, OVF can occur)
	1	0	Capture mode (falling edges, counter running, OVF can occur)
	1	1	Capture mode (rising and falling edges, counter running, OVF can occur)

.3	Timer 2 Counter Clear Bit
	0	No effect (when write)
	1	Clear T2 counter, T2CNT (when write)
.2	Timer 2 Overflow Interrupt Enable Bit (note)
	0	Disable T2 overflow interrupt
	1	Enable T2 overflow interrupt
.1	Timer 2 Match/Capture Interrupt Enable Bit
	0	Disable T2 match/capture interrupt
	1	Enable T2 match/capture interrupt
.0	Timer 2 Match/Capture Interrupt Pending Flag Bit
	0	No T2 match/capture interrupt pending (when read)
	0	Clear T2 match/capture interrupt pending condition (when write)
	1	T2 match/capture interrupt is pending (when read)
	1	No effect (when write)

NOTE: A timer 2 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 2 match/ capture interrupt, IRQ3, vector F2H, must be cleared by the interrupt service routine (S/W).

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