Samsung S3F80JB manual Clkcon System Clock Control Register D4H Set1 Bank0

S3F80JBCONTROL REGISTERS

CLKCON — System Clock Control Register D4H Set1 Bank0

Bit Identifier

Reset Value

Read/Write

Addressing Mode

.7 – .5

.4 and .3

.7	.6	.5	.4	.3	.2	.1	.0
0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Register addressing mode only

Not used for S3F80JB

CPU Clock (System Clock) Selection Bits (1)

00 fOSC/16

01 fOSC/8

10 fOSC/2

1 1 fOSC (non-divided)

.2 – .0	Subsystem Clock Selection Bits (2)
	1	0	1	Not used for S3F80JB.
	Other value			Select main system clock (MCLK)

NOTES:

1.After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4.

2.These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The S3F80JB uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.

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