Samsung S3F80JB manual Cmod Comparator Mode Register E9H Set1 Bank1, Comparator Enable Bit

CONTROL REGISTERSS3F80JB

CMOD — Comparator Mode Register E9H Set1 Bank1

Bit Identifier

Reset Value

Read/Write

Addressing Mode

.7

.7	.6	.5	.4	.3	.2	.1	.0
0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Register addressing mode only

Comparator Enable Bit

0Comparator operation disable

1Comparator operation enable

.6	Conversion Timer Control Bit
	0	8	⋅ 27/ fOSC, 256￿ at 8 MHz
	1	8	⋅ 24/ fOSC, 32￿ at 8 MHz
.5	External Reference Selection Bit
	0	Internal reference, CIN0-3: Analog input
	1	External reference, CIN0-2: Analog input, CIN3: Reference input

.4

.3 – .0

Not used for S3F80JB.

Reference Voltage Selection Bits

Selected VREF = VDD ⋅ (N + 0.5)/16, N = 0 to 15

NOTE: You can select the number of analog input pin for your purpose by setting the CMPSEL.

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