Samsung S3F80JB manual Timer 2 Counter Register Low Byte, Timer 2 Data Register High Byte

S3F80JB RESET

Table 8-4. Set 1, Bank 1 Register Values After Reset

Register Name	Mnemonic	Address				Bit Values After Reset
		Dec	Hex	7	6		5	4	3	2	1	0
LVD Control Register	LVDCON	224	E0H	–	–		–	–	–	–	–	0
Port 3 [4:5] Control Register	P345CON	225	E1H	0	1		0	1	0	0	0	0
Port 4 Control Register (High Byte)	P4CONH	226	E2H	1	1		1	1	1	1	1	1
Port 4 Control Register (Low Byte)	P4CONL	227	E3H	1	1		1	1	1	1	1	1
Timer 2 Counter Register (High Byte)	T2CNTH	228	E4H	0	0		0	0	0	0	0	0
Timer 2 Counter Register (Low Byte)	T2CNTL	229	E5H	0	0		0	0	0	0	0	0
Timer 2 Data Register (High Byte)	T2DATAH	230	E6H	1	1		1	1	1	1	1	1
Timer 2 Data Register (Low Byte)	T2DATAL	231	E7H	1	1		1	1	1	1	1	1
Timer 2 Control Register	T2CON	232	E8H	0	0		0	0	0	0	0	0
Comparator Mode Register	CMOD	233	E9H	0	0		0	0	0	0	0	0
Comparison Result Register	CMPREG	234	EAH	0	0		0	0	0	0	0	0
Comparator Input Selection Register	CMPSEL	235	EBH	–	–		–	–	0	0	0	0
Flash Memory Sector Address	FMSECH	236	ECH	0	0		0	0	0	0	0	0
Register (High Byte)
Flash Memory Sector Address	FMSECL	237	EDH	0	0		0	0	0	0	0	0
Register (Low byte)
Flash Memory User Programming	FMUSR	238	EEH	0	0		0	0	0	0	0	0
Enable Register
Flash Memory Control Register	FMCON	239	EFH	0	0		0	0	–	–	–	0

NOTES:

1.P345CON will be initialized as “50H” to set P3.4 and P3.5 into open drain output mode after reset operation.

2.S3F80JB has P4CONH, P4CONL and P4CON as port4 control registers. P4CONH and P4CONL will be initialized as the C-MOS input with pull up mode after reset. On the other hand, P4CON will be initialized as open-drain output mode. After reset, status of port4 is decided by P345CON.0 bit. So port4 reset status will be initialized as open-drain output mode.

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