S3F80JB

CLOCK CIRCUITS

 

 

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in address D4H, Set1, Bank0. It is read/write addressable and has the following functions:

— Oscillator frequency divide-by value

The CLKCON.7 - .5 and CLKCON.2- .0 Bit are not used in S3F80JB. After a reset, the main oscillator is activated, and the fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fOSC, fOSC/2, fOSC/8 or fOSC/16.

System Clock Control Register (CLKCON)

D4H, Set 1, Bank 0, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0 LSB

Not used

Divide-by selection bits for CPU clock frequency

Not used 00 = fosc/16 01 = fosc/8 10 = fosc/2

11 = fosc (non-divided)

Figure 7-4. System Clock Control Register (CLKCON)

7-3

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Samsung S3F80JB manual System Clock Control Register Clkcon