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Samsung S3F80JB manual Relative Address Mode RA, Relative Addressing

Models: S3F80JB

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S3F80JB	ADDRESSING MODES

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.

Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Displacement

Current Instruction		OPCODE

Current

PC Value +

Signed Displacement Value

Sample Instructions:
JR	ULT,$+OFFSET	; Where OFFSET is a value in the range +127 to -128

Figure 3-13. Relative Addressing

3-13

Image 66

Samsung S3F80JB manual Relative Address Mode RA, Relative Addressing

Contents

S3F80JB Important Notice Reset Part Programming ModelTable of Contents Interrupt Structure Reset Summary Table of Back-Up Mode, Stop Mode, and Reset Status10-2 Timer10-1 10-315-3 Flash Memory User Programming Enable Register Fmusr 15-615-1 15-5List of Figures Title Number10-8 10-510-7 10-912-2 17-3 Typical Low-Side Driver Sink Characteristics17-6 Typical High-Side Driver Source Characteristics 12-518-2 18-3 Typical Low-Side Driver Sink Characteristics18-6 Typical High-Side Driver Source Characteristics 18-4Reset Condition in Stop Mode When Ipor / LVD Control Bit is List of Tables17-13 17-317-6 18-3Description Chapter ResetChapter Basic Timer and Timer Chapter Address SpacesRegister Full Register Name Identifier Instruction Full Register Name Mnemonic POP NextNOP PopudS3C8/S3F8-SERIES Microcontrollers S3F80JB MicrocontrollerFeatures CPUBlock Diagram 32-PIN Package Block Diagram 32-pinBlock Diagram 44-PIN Package Block Diagram 44-pinPin Assignment Diagram 32-Pin SOP Package PIN AssignmentsPIN Assignments S3F80JB44-QFP Pin Descriptions of 32-SOP Circuit 32 Pin Shared Names Pin Descriptions of 44-QFP Circuit 44 Pin Shared Names P3.1 Port with bit-programmable pin. Configurable to PIN Circuits Pin Circuit Type 1 Port 0 and Port2PIN Circuits Pin Circuit Type 2 Port 1, Port4, P3.4 and P3.5Pin Circuit Type 3 P3.0 Pin Circuit Type 4 P3.1 10. Pin Circuit Type 6 nRESET Address Space OverviewProgram Memory Program Memory Address SpaceSmart Option Smart OptionS3F80JB Address Spaces Register Architecture Summary of S3F80JB Register Type Number of BytesTotal Addressable Bytes 333 Internal Register File Organization Register page Pointer PP Register Page Pointer PPRegister SET Prime Register Space Set 1, Set 2, and Prime Area Register MapWorking Registers Byte Working Register Areas SlicesUsing the Register Pointers Programming TIP Setting the Register PointersR0,R2 #80H RP0 ← 80HR0,R1 ← R0 + R0,R3Register Addressing Bit Register Pair10. Register File Addressing Common Working Register Area C0H-CFH RP1 → C8H-CFHProgramming TIP Addressing the Common Working Register Area ExampleBIT Working Register Addressing 12 -Bit Working Register Addressing 14 -Bit Working Register Addressing 15 -Bit Working Register Addressing Example System and User Stacks Stack OperationsStack Pointers SPL Push RP1 SPL,#0FFH SPL ← FFHPush RP0 POP RP1Addressing Modes Register Addressing Mode R Register AddressingIndirect Register Addressing Mode IR Indirect Register Addressing to Register FileIndirect Register Addressing Mode Indirect Register Addressing to Program MemoryIndirect Working Register Addressing to Register File LCD Indexed Addressing Mode Indexed Addressing to Register FileIndexed Addressing Mode Next 2 BitsIndexed Addressing to Program or Data Memory Direct Address Mode DA 10. Direct Addressing for Load InstructionsDirect Address Mode 11. Direct Addressing for Call and Jump InstructionsIndirect Address Mode IA 12. Indirect AddressingRelative Address Mode RA 13. Relative AddressingImmediate Mode IM 14. Immediate AddressingControl Registers T0DATA T0CNTD0H D1HMapped Registers Register Name Mnemonic Decimal Hex Register Description Format Watchdog Timer Function Enable Bits for System Reset Btcon Basic Timer Control Register D3H Set1 Bank0Bit Identifier Reset Value Read/Write Addressing Mode Basic Timer Input Clock Selection BitsCacon Counter a Control Register F3H Set1 Bank0 Clkcon System Clock Control Register D4H Set1 Bank0 CPU Clock System Clock Selection BitsSubsystem Clock Selection Bits Conversion Timer Control Bit Cmod Comparator Mode Register E9H Set1 Bank1Comparator Enable Bit External Reference Selection BitP2.6 Function Selection Bit Cmpsel Comparator Input Selection Register EBH Set1 Bank1P2.7 Function Selection Bit P2.5 Function Selection BitEMT External Memory Timing Register Note FEH Set1 Bank0 Flags System Flags Register D5H Set1 Bank0 Flash Memory Mode Selection Bits Fmcon Flash Memory Control Register EFH Set1 Bank1Operation stop Operation start auto clear bit Flash Memory User Programming Enable Bits Flash Memory Sector Address High ByteFlash Memory Sector Address Low Byte Interrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or OverflowInterrupt Level 2 IRQ2 Enable Bit Counter a Interrupt Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or OverflowInstruction Pointer Address High Byte IPH Instruction Pointer High Byte DAH Set1 Bank0IPL Instruction Pointer Low Byte DBH Set1 Bank0 Instruction Pointer Address Low ByteIPR Interrupt Priority Register FFH Set1 Bank0 Not pending IRQ Interrupt Request Register DCH Set1 Bank0Not pending Pending Level 2 IRQ2 Request Pending Bit Counter a InterruptLVD Flag 2.3V Indicator Bit Lvdcon LVD Control Register E0H Set1 Bank1VDD ≥ Lvdflag Level VDD Lvdflag Level P0.5/INT4 Mode Selection Bits P0.7/INT4 Mode Selection BitsP0.6/INT4 Mode Selection Bits P0.4/INT4 Mode Selection BitsP0.1/INT1 Mode Selection Bits P0.3/INT3 Mode Selection BitsP0.2/INT2 Mode Selection Bits P0.0/INT0 Mode Selection BitsP0.5 External Interrupt INT4 Enable Bit P0.7 External Interrupt INT4 Enable BitP0.6 External Interrupt INT4 Enable Bit P0.4 External Interrupt INT4 Enable BitP0.5 External Interrupt INT4 Pending Flag Bit P0.7 External Interrupt INT4 Pending Flag Bit see NoteP0.6 External Interrupt INT4 Pending Flag Bit P0.4 External Interrupt INT4 Pending Flag BitP0.5 Pull-up Resistor Enable Bit P0.7 Pull-up Resistor Enable BitP0.6 Pull-up Resistor Enable Bit P0.4 Pull-up Resistor Enable BitP1.5 Mode Selection Bits P1.7 Mode Selection BitsP1.6 Mode Selection Bits P1.4 Mode Selection BitsP1.1 Mode Selection Bits P1.3 Mode Selection BitsP1.2 Mode Selection Bits P1.0 Mode Selection BitsP2.5/INT9 Mode Selection Bits P2.7/INT9 Mode Selection BitsP2.6/INT9 Mode Selection Bits P2.4/INT9 Mode Selection BitsP2.1/INT6 Mode Selection Bits P2.3/INT8 Mode Selection BitsP2.2/INT7 Mode Selection Bits P2.0/INT5 Mode Selection BitsP2.5 External Interrupt INT9 Enable Bit P2.7 External Interrupt INT9 Enable BitP2.6 External Interrupt INT9 Enable Bit P2.4 External Interrupt INT9 Enable BitP2.5 External Interrupt INT9 Pending Flag Bit P2.7 External Interrupt INT9 Pending Flag Bit see NoteP2.6 External Interrupt INT9 Pending Flag Bit P2.4 External Interrupt INT9 Pending Flag BitP2.5 Pull-up Resistor Enable Bit P2.7 Pull-up Resistor Enable BitP2.6 Pull-up Resistor Enable Bit P2.4 Pull-up Resistor Enable BitP3CON Port 3 Control Register EFH Set1 Bank0 P3CON Each Function Description and Assignment to P3.0-P3.3P345CON Port345 Control Register E1H Set1 Bank1 P3.5 Mode Selection BitsP3.4 Mode Selection Bits Port 4 Control Register Selection BitP4CON Port 4 Control Register F0H Set1 Bank0 P4.5 Mode Selection Bits P4.7 Mode Selection BitsP4.6 Mode Selection Bits P4.4 Mode Selection BitsP4.1 Mode Selection Bits P4.3 Mode Selection BitsP4.2 Mode Selection Bits P4.0 Mode Selection BitsSource Register Page Selection Bits PP Register Page Pointer DFH Set1 Bank0Destination page 0 See Note Source page 0 See NoteRegister Pointer 0 Address Value RP0 Register Pointer D6H Set1 Bank0RP1 Register Pointer D7H Set1 Bank0 Register Pointer 1 Address ValueStopcon Stop Control Register FBH Set1 Bank0 Stop Control Register Enable BitsSPL Stack Pointer Low Byte D9H Set1 Bank0 Stack Pointer Address Low ByteGlobal Interrupt Enable Bit SYM System Mode Register DEH Set1 Bank0Fast Interrupt Enable Bit Tri-State External Interface Control BitT0CON- Timer 0 Control Register D2H Set 1 Bank0 T1CON Timer 1 Control Register FAH Set1 Bank0 T2CON Timer 2 Control Register E8H Set1 Bank1 Levels VectorsSources Interrupt Types S3C8/S3F8-Series Interrupt TypesS3F80JB Interrupt Structure S3F80JB Interrupt Structure Interrupt Vector Addresses ROM Vector Address AreaInterrupt Priority FCHD8H ENABLE/DISABLE Interrupt Instructions EI, DI SYSTEM-LEVEL Interrupt Control RegistersInterrupt Control Register Overview Function Description Interrupt Function Diagram Interrupt Processing Control PointsPeripheral Interrupt Control Registers System Mode Register SYM System Mode Register SYMInterrupt Mask Register IMR Interrupt Mask Register IMRInterrupt Priority Register IPR Interrupt Request Priority GroupsInterrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQOverview Pending Bits Cleared by the Service RoutineInterrupt Pending Function Types Pending Bits Cleared Automatically by HardwareInterrupt Service Routines Interrupt Source Polling SequenceInstruction Pointer IP Generating Interrupt Vector AddressesNesting of Vectored Interrupts Fast Interrupt ProcessingFast Interrupt Processing Procedure for Initiating Fast InterruptFast Interrupt Service Routine Programming GuidelinesData Types Addressing ModesLded LDELDC LdcdLogic Instructions Bit Manipulation Instructions CPU Control Instructions Flags Register Flags System Flags Register FlagsFlag Descriptions Instruction Set Symbols Instruction SET NotationFlag Notation Conventions @Rn or @reg reg = 0-255, n = Immediate addressing mode #data data =Immediate long addressing mode #data data = range Irr Indirect working register pair only @RRp p = 0, 2Opcode Quick Reference Opcode MAP Lower Nibble HEXR1,IM Djnz INC NextR1,R2 R2,R1 Djnz INC NOPCondition Codes Condition Codes Binary Mnemonic Description Flags SetInstruction Descriptions Format Bytes Cycles ADC Add with carryFlags Dst SrcADD Add Logical Flags Unaffected Set if the result is 0 cleared otherwiseAlways cleared to Band Bit BCP Bit Compare BCPOperation Bitc Bit Complement BitcHex Dst Bitr Bit Reset Bitr dst.b Operation dstb ←Format Bits Bit Set Bits dst.b Operation dstb ←BOR Bit or BORBtjrf Bit Test, Jump Relative on False Example Given R1 = 07HBtjrf SKIP,R1.3 Btjrt Bit Test, Jump Relative on True Btjrt SKIP,R1.1Bxor Bit XOR R1,01H.1 R1 = 06H, register 01H = 03HCall Call Procedure Call@SP PCL PCH Operation C ← not C CCF Complement Carry FlagCCF Complemented No other flags are affectedCLR Clear CLR dst Operation dst ←00H Register 00H COM Complement COMCP Compare INC Skip LDCpije Compare, Increment, and Jump on Equal CpijeIf dst src 0, PC ← PC + RA Cpijne Compare, Increment, and Jump on Non-EqualCpijne InstructionDA Decimal Adjust DAdst Operation dst ← DA dstBits 3CH R1,R0R1 ← 3CH + @R1 @R1 ← Leave the value 31 BCD in address 27H @R1Dst Operation ← dst DEC DecrementDEC Opc Dst Examples Given R1 = 03H and register 03H = 10HDecw Decrement Word DecwDI Disable Interrupts Operation SYM 0 ←No flags are affected DIV Divide Unsigned Operation dst ÷ srcJump taken No jump Djnz Decrement and Jump if Non-ZeroDjnz r,dst Operation r ← r SRP #0C0H Djnz R1,LOOPEI Enable Interrupts Operation SP Enter EnterEnter @SP @IPOperation IP Exit ExitExit @SPIdle Idle Operation IdleINC dst Operation dst ← dst + Contents of the destination operand are incremented by oneINC Increment = 1CHIncw RR0 Incw Increment WordIncw Loop Incw RR0Flags ← @SP PC ↔ IP Iret Interrupt ReturnIret Flags ← FlagsJP Jump LabelwJR Jump Relative Example Given The carry flag = 1 and Labelx = 1FF7HLabelx → PC = 1FF7H LD Load Dst ← src0AH = 0FFH, R1 = 0AHRegister 31H = 0AH, R0 = 01H, R1 = 0AH Dst Examples Given R0 = 06H and general register 00H = 05H LDB Load BitLDB R0,00H.2 07H, register 00H 05HLDC/LDE dst,src Operation dst ← src Addr ModeLDC/LDE Load Memory XL L XL HLDC/LDE ExamplesLDCD/LDED Load Memory and Decrement LDCD/LDED dst,src Operation dst ← srcRr ← rr + LDCI/LDEI Load Memory and IncrementLDCI/LDEI dst,src Operation dst ← src Into R8 and RR6 is incremented by one RR6 ← RR6 +LDCPD/LDEPD Load Memory with Pre-Decrement LdcpdOperation rr ← rr LDCPI/LDEPI Load Memory with Pre-Increment LdcpiOperation rr ← rr + LDW Load Word RR IMLLDW RR6,RR4 Operation dst ← dst ⋅ src Mult Multiply UnsignedMult dst,src ClearedNext Next NextOperation PC ← @ IP When the instruction NOP No OperationNOP Or Logical or POP Pop From Stack POP dst Operation dst ← @SP00H Register 00H 55H, SP = 00FCH Popud Pop User Stack Decrementing Popud dst,srcPopui Pop User Stack Incrementing Popui dst,srcSPH = 0FFH, SPL = 0FFH Push Push To StackPush src Operation SP ← SP 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFHIR ← IR Pushud Push User Stack DecrementingPushud Decremented stack pointerPushui Push User Stack Incrementing Pushui dst,src Operation IR ← IR +RCF Reset Carry Flag RCFFlags Cleared to Operation PC ← @SP RET ReturnRET PC = 101AH, SP = 00FEHDst n + 1 ← dst n, n = RL Rotate LeftDst 0 ← dst Set if the result bit 7 is set cleared otherwiseRLC Rotate Left Through Carry RLCOperation C ← dst RR Rotate RightRR dst Rotation cleared otherwiseDst 7 ← C RRC Rotate Right Through CarryRRC 00H Register 00H 2AH, C =Operation Bank ← SB0 Select BankSB0 StatementSB1 Select Bank SB1SBC Subtract With Carry Always set toSet otherwise, indicating a borrow Format Bytes Cycles Set to No other flags are affected SCF Set Carry FlagSCF Sets the carry flag to logic oneSRA Shift Right Arithmetic SRA dst00H Register 00H 0CD, C = SRP0 SRP/SRP0/SRP1 Set Register PointerSRP SRP1Stop Stop Operation StopSUB Subtract SUBSet otherwise indicating a borrow Format Bytes Cycles Flags Undefined Set if the result is 0 cleared otherwise Swap Swap NibblesSwap dst 00H Register 00H 0E3HR0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = TCM Test Complement Under MaskR0,R1 = 0C7H, R1 = 02H, Z = 00H,01H Register 00H = 2BH, register 01H = 02H, Z =TMdst,src Always reset toTM Test Under Mask Operation dst and srcWFI Wait For Interrupt WFIOpc 4n 3F XOR Logical Exclusive or XOR7FH Clock Circuits System Clock CircuitClock Status During POWER-DOWN Modes System Clock Circuit DiagramSystem Clock Control Register Clkcon System Clock Control Register ClkconReset Reset SourcesEIexternal interrupt enable Reset Sources of The S3F80JBReset Block Diagram of The S3F80JB Watch DOG Timer Reset Reset MechanismExternal Reset PIN LVD ResetInternal POWER-ON Reset Internal Power-On Reset CircuitTiming Diagram for Internal Power-On Reset Circuit Reset Timing Diagram for The S3F80JB in Stop mode by Ipor External Interrupt ResetReset Source Stop Error Detection & RecoveryVreset Slope of V DDPOWER-DOWN Modes Idle ModeIdle Mode Release BACK-UP Mode Block Diagram for Back-up ModeStop Mode Programming TIP To Enter Stop ModeUsing Ipor to Release Stop Mode Sources to Release Stop ModeUsing nRESET Pin to Release Stop Mode Using LVD to Release Stop ModeSED&R Stop Error Detect and Recovery System Reset Operation Hardware Reset Values DecTimer 1 Control Register Timer 1 Data Register High ByteTimer 1 Data Register Low Byte Dec HexTimer 2 Data Register Low Byte Timer 2 Counter Register Low ByteTimer 2 Data Register High Byte Timer 2 Control RegisterStop Ipor IporLVD SED&RP2PUR Recommendation for Unusued Pins← # 0FFH Connect to VSSStopcon ← # A5H Summary Table of BACK-UP MODE, Stop MODE, and Reset StatusSummary of Each Mode Item/Mode Back-up Reset Status Stop LD STOPCON,#0A5HO Ports Assigned individually as analog input pin for comparator S3F80JB Port Configuration Overview 44-QFPPort Configuration Options P3.0-P3.1S3F80JB Port Configuration Overview 32-SOP Port Data Registers S3F80JB I/O Port Data Register FormatPULL-UP Resistor Enable Registers Pull-up Resistor Enable Registers Port 0 and Port 2 onlyBasic Timer BT TimerBasic Timer Control Register Btcon Basic Timer Control Register BtconBasic Timer Function Description Watch-dog Timer FunctionOscillation Stabilization Interval Timer Function Timer 0 Control Register T0CON Timer 0 Control Register T0CON Timer 0 Function Description Timer 0 Interrupts IRQ0, Vectors FAH and FCHInterval Timer Mode Pulse Width Modulation Mode Simplified Timer 0 Function Diagram PWM ModeCapture Mode Simplified Timer 0 Function Diagram Capture ModeBasic Timer and Timer 0 Block Diagram CLR SPL Programming TIP Configuring the Basic TimerCLR SYM Main BTCON,#52HProgramming TIP Programming Timer ULT,NO200MSSET Bits NO200MSSETT0OVER Iret Timer Timer 1 Overflow Interrupt Timer 1 Capture InterruptTimer 1 Match Interrupt Simplified Timer 1 Function Diagram Interval Timer ModeTimer 1 Block Diagram Timer 1 Control Register T1CON Timer 1 Control Register T1CONTimer 1 Registers T1CNTH, T1CNTL, T1DATAH, T1DATAL Counter a Counter a Block Diagram Counter a Control Register Cacon Counter a Control Register CaconMethod 2 When Caof = Counter a Pulse Width CalculationsCounter a Output Flip-Flop Waveforms in Repeat Mode Through P3.1 CADATAL,# Programming TIP To generate a one-pulse signal through P3.1CADATAH,# Set 40 ms Set any value except 00H13-1 Timer 2 Overflow Interrupt Timer 2 Capture InterruptTimer 2 Match Interrupt Simplified Timer 2 Function Diagram Interval Timer ModeTimer 2 Block Diagram Timer 2 Control Register T2CON Timer 2 Control Register T2CONTimer 2 Registers T2CNTH, T2CNTL, T2DATAH, T2DATAL Comparator Comparator Block Diagram for The S3F80JB Conversion Characteristics Comparator OperationComparator Mode Register Cmod Comparator Result Register Cmpreg Flash ROM Configuration Embedded Flash Memory InterfaceUser Program Mode Tool Program ModePin No Function Isptm ON-BOARD Programming Sector 15-4 Area of ISP Sector ISP Sector Size ISP Reset Vector and ISP Sector SizeISP Sector Size BitFlash Memory Control Registers User Program Mode Flash Memory User Programming Enable Register FmusrFlash Memory Control Register Fmcon Flash Memory Sector Address Registers Flash Memory Sector Address Register FmsechSector Configurations in User Program Mode Sector EraseSector Erase Procedure in User Program Mode Sector Erase Flowchart in User Program ModeProgramming TIP Sector Erase Case1. Erase one sector Nocarry SectoreraseBtjrf FLAGS.7,NOCARRY Erasestart SB1 FMUSR,#0A5HProgram procedure in user program mode ProgrammingByte Program Flowchart in a User Program Mode 10. Program Flowchart in a User Program Mode Programming TIP Programming Case1 -Byte Programming Case2. Programming in the same sectorCall Wrbyte WRINSECTOR2LD FMSECH,#01H WRINSECTOR50 FMSECH,#19HLoop LDC ReadingProgramming TIP Reading NZ,LOOPHard Lock Protection Programming TIP Hard Lock ProtectionFMCON,#01100001B LVD LVD FlagResistor String LOW Voltage Detector Control Register Lvdcon Low Voltage Detect Control Register LvdconElectrical Data 4MHz Parameter Symbol Conditions Min Typ Max Unit Parameter Symbol Conditions Rating UnitD.C. Electrical Characteristics Absolute Maximum RatingsVout = 0 Leakage Current All output pins Pull-Up Leakage Current All input pins except ILIH2 and XoutLeakage Current All output pins Output Low Output LowData Retention Supply Voltage in Stop Mode Characteristics of Low Voltage Detect CircuitParameter Symbol Conditions Min Typ Max UnitTypical Low-Side Driver Sink Characteristics P3.1 only Typical High-Side Driver Source Characteristics P3.1 only Typical VDD-VOHVDD=3.3V Stop Mode Release Timing When Initiated by a Reset A.C. Electrical Characteristics 10. Input Timing for External Interrupts Port 0 and Port Oscillation Characteristics Oscillator Clock Circuit Conditions Min Typ Max UnitOscillation Stabilization Time When released by a reset 216/f StabilizationWait time TWAIT when released by an interrupt TA = 25 C to + 85 C, VDD = 3.6Chip Erasing Time 100 Data Access TimeSector Erasing Time VDD = 2.0 250 Number of Writing/Erasing FNwe 10,000Electrical Data 8MHZ VDD = 2.35 V, IOH = 6mA TA = 25 C to + 85 C, VDD = 1.95 V to 3.6Fosc = 8 MHz Input High Voltage VDD = 2.35 V, IOH = 2.2mA P3.0 and P2.0-2.3Leakage Current All output pins Pull-Up Resistors Leakage Current All input pins except ILIH2Leakage Current All input pins except ILIL2 VDD = 2.35 V, IOL = 12mAStop Mode LVD OFF, V DD = 3.6 LVD ON, V DD = 3.6 Operating Mode DD = 3.6 MHz crystalIdle Mode DD =3.6 MHz crystal For Back-Up Mode Low Level Detect VoltageVddv Typical VDD-VOHVDD=3.3V Typical VDD-VOHVDD=3.3V VDD-VOHVIOHmA 18-8 18-9 18-10 Comparator Electrical Characteristics Parameter Symbol Condition Min Typ Max UnitsTA = -25 C to + 85 C, VDD = 3.6 Flash Erase/Write/Read Voltage Fewrv 18-14 Pin SOP Package Dimension SOP-450AQFP-1010B Target Boards Programming Socket AdapterTB80JB Target Board Configuration TB80JB Target BoardVCC, GND, S Components Consisting of S3F80JB Target Board Block SymbolsJ1A IDLE, Stop LEDJP# Idle LEDStop LED Pin Connector Pin Assignment for TB80JB GW-PRO2 Series In-Circuit EmulatorOTP/MTP Programmer Development Tools SuppliersOTP/MTP Programmer Writer SPW2+ SeminixGW-PRO2 Package Marking Check One For what kind of product will you be using this order?Product description Customer sample Risk orderOrder Quantity and Delivery Schedule Risk Order InformationCustomer Risk Order Agreement Delivery Date s Quantity Comments SignaturesFlash Application Notes VDD S3F80JB Important Note For Serial Programming Mode S3F80JB/9 is needed to nRESET pin = 0GND & Test pin = 1VDDWhen nRESET pin = 1VDD & Test pin = 0GND For Normal Operating ModeS3F80JB/9 is needed to nRESET pin = 1VDD & Test pin = 0GND Timing DiagramWhen Test PIN = 1VDD ¾ When S3F80JB¾ When S3F80J9