Samsung S3F80JB manual P0.7 External Interrupt INT4 Pending Flag Bit see Note

CONTROL REGISTERSS3F80JB

P0PND — Port 0 External Interrupt Pending Register F2H Set1 Bank0

Bit Identifier

Reset Value

Read/Write

Addressing Mode

.7

.6

.7	.6	.5	.4	.3	.2	.1	.0
0	0	0	0	0	0	0	0
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

Register addressing mode only

P0.7 External Interrupt (INT4) Pending Flag Bit (see Note)

0No P0.7 external interrupt pending (when read)

1P0.7 external interrupt is pending (when read)

P0.6 External Interrupt (INT4) Pending Flag Bit

0No P0.6 external interrupt pending (when read)

1P0.6 external interrupt is pending (when read)

.5	P0.5 External Interrupt (INT4) Pending Flag Bit
	0	No P0.5 external interrupt pending (when read)
	1	P0.5 external interrupt is pending (when read)
.4	P0.4 External Interrupt (INT4) Pending Flag Bit
	0	No P0.4 external interrupt pending (when read)
	1	P0.4 external interrupt is pending (when read)
.3	P0.3 External Interrupt (INT3) Pending Flag Bit
	0	No P0.3 external interrupt pending (when read)
	1	P0.3 external interrupt is pending (when read)
.2	P0.2 External Interrupt (INT2) Pending Flag Bit
	0	No P0.2 external interrupt pending (when read)
	1	P0.2 external interrupt is pending (when read)
.1	P0.1 External Interrupt (INT1) Pending Flag Bit
	0	No P0.1 external interrupt pending (when read)
	1	P0.1 external interrupt is pending (when read)
.0	P0.0 External Interrupt (INT0) Pending Flag Bit
	0	No P0.0 external interrupt pending (when read)
	1	P0.0 external interrupt is pending (when read)

NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt pending flag (P0PND.7–0) has no effect.

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