Samsung S3F80JB manual Logical, Flags Unaffected Set if the result is 0 cleared otherwise

INSTRUCTION SETS3F80JB

AND — Logical AND

AND dst,src

Operation: dst ← dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.

Flags:	C:	Unaffected.
	Z:	Set if the result is "0"; cleared otherwise.
	S:	Set if the result bit 7 is set; cleared otherwise.
	V:	Always cleared to "0".
	D:	Unaffected.
	H:	Unaffected.

Format:
Bytes Cycles	Opcode	Addr Mode
	(Hex)	dst	src

opc	dst src
opc	src	dst

2	4	52	r	r
	6	53	r	lr
3	6	54	R	R
	6	55	R	IR

opc

dst

src

3 6 56 R IM

Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

AND	R1,R2	→	R1	= 02H, R2 = 03H
AND	R1,@R2	→	R1	= 02H, R2 = 03H
AND	01H,02H	→	Register 01H		= 01H, register 02H = 03H
AND	01H,@02H	→	Register 01H		=	00H, register 02H = 03H
AND	01H,#25H	→	Register 01H		=	21H

In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

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