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Samsung S3F80JB manual Oscillation Stabilization Time, TA = -25 C to + 85 C, VDD = 3.6

Models: S3F80JB

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ELECTRICAL DATA (8MHz)	S3F80JB

Table 18-9. Oscillation Stabilization Time

(TA = –25 °C to + 85 °C, VDD = 3.6 V)

Oscillator			Test Condition	Min	Typ	Max	Unit
Main crystal	fOSC > 400 kHz			–	–	20	ms
Main ceramic	Oscillation stabilization occurs when VDD is			–	–	10	ms
	equal to the minimum oscillator voltage range.
External clock	XIN input High and Low width (tXH, tXL)			25	–	500	ns
(main system)
Oscillator	t	WAIT	when released by a reset (1)	–	216/f	–	ms
stabilization		WAIT			OSC
stabilization
wait time

	tWAIT when released by an interrupt (2)			–	–	–	ms

NOTES:

1.fOSC is the oscillator frequency.

2.The duration of the oscillation stabilization time (tWAIT) when it is released by an interrupt is determined by the setting in the basic timer control register, BTCON.

18-12

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Samsung S3F80JB manual Oscillation Stabilization Time, TA = -25 C to + 85 C, VDD = 3.6

Contents

S3F80JB Important Notice Part Programming Model ResetTable of Contents Interrupt Structure Summary Table of Back-Up Mode, Stop Mode, and Reset Status Reset10-1 Timer10-2 10-315-1 Flash Memory User Programming Enable Register Fmusr 15-615-3 15-5Title Number List of Figures10-7 10-510-8 10-917-6 Typical High-Side Driver Source Characteristics 17-3 Typical Low-Side Driver Sink Characteristics12-2 12-518-6 Typical High-Side Driver Source Characteristics 18-3 Typical Low-Side Driver Sink Characteristics18-2 18-4List of Tables Reset Condition in Stop Mode When Ipor / LVD Control Bit is17-6 17-317-13 18-3Chapter Basic Timer and Timer Chapter ResetDescription Chapter Address SpacesRegister Full Register Name Identifier Instruction Full Register Name Mnemonic NOP NextPOP PopudS3F80JB Microcontroller S3C8/S3F8-SERIES MicrocontrollersCPU FeaturesBlock Diagram 32-pin Block Diagram 32-PIN PackageBlock Diagram 44-pin Block Diagram 44-PIN PackagePIN Assignments Pin Assignment Diagram 32-Pin SOP PackageS3F80JB PIN Assignments44-QFP Pin Descriptions of 32-SOP Circuit 32 Pin Shared Names Pin Descriptions of 44-QFP Circuit 44 Pin Shared Names P3.1 Port with bit-programmable pin. Configurable to Pin Circuit Type 1 Port 0 and Port2 PIN CircuitsPin Circuit Type 2 Port 1, Port4, P3.4 and P3.5 PIN CircuitsPin Circuit Type 3 P3.0 Pin Circuit Type 4 P3.1 10. Pin Circuit Type 6 nRESET Overview Address SpaceProgram Memory Address Space Program MemorySmart Option Smart OptionS3F80JB Address Spaces Summary of S3F80JB Register Type Number of Bytes Register ArchitectureTotal Addressable Bytes 333 Internal Register File Organization Register Page Pointer PP Register page Pointer PPRegister SET Set 1, Set 2, and Prime Area Register Map Prime Register SpaceByte Working Register Areas Slices Working RegistersProgramming TIP Setting the Register Pointers Using the Register PointersR0,R1 ← R0 + #80H RP0 ← 80HR0,R2 R0,R3Bit Register Pair Register Addressing10. Register File Addressing RP1 → C8H-CFH Common Working Register Area C0H-CFHExample Programming TIP Addressing the Common Working Register AreaBIT Working Register Addressing 12 -Bit Working Register Addressing 14 -Bit Working Register Addressing 15 -Bit Working Register Addressing Example Stack Operations System and User StacksStack Pointers SPL Push RP0 SPL,#0FFH SPL ← FFHPush RP1 POP RP1Addressing Modes Register Addressing Register Addressing Mode RIndirect Register Addressing to Register File Indirect Register Addressing Mode IRIndirect Register Addressing to Program Memory Indirect Register Addressing ModeIndirect Working Register Addressing to Register File LCD Indexed Addressing to Register File Indexed Addressing ModeNext 2 Bits Indexed Addressing ModeIndexed Addressing to Program or Data Memory 10. Direct Addressing for Load Instructions Direct Address Mode DA11. Direct Addressing for Call and Jump Instructions Direct Address Mode12. Indirect Addressing Indirect Address Mode IA13. Relative Addressing Relative Address Mode RA14. Immediate Addressing Immediate Mode IMControl Registers D0H T0CNTT0DATA D1HMapped Registers Register Name Mnemonic Decimal Hex Register Description Format Bit Identifier Reset Value Read/Write Addressing Mode Btcon Basic Timer Control Register D3H Set1 Bank0Watchdog Timer Function Enable Bits for System Reset Basic Timer Input Clock Selection BitsCacon Counter a Control Register F3H Set1 Bank0 CPU Clock System Clock Selection Bits Clkcon System Clock Control Register D4H Set1 Bank0Subsystem Clock Selection Bits Comparator Enable Bit Cmod Comparator Mode Register E9H Set1 Bank1Conversion Timer Control Bit External Reference Selection BitP2.7 Function Selection Bit Cmpsel Comparator Input Selection Register EBH Set1 Bank1P2.6 Function Selection Bit P2.5 Function Selection BitEMT External Memory Timing Register Note FEH Set1 Bank0 Flags System Flags Register D5H Set1 Bank0 Fmcon Flash Memory Control Register EFH Set1 Bank1 Flash Memory Mode Selection BitsOperation stop Operation start auto clear bit Flash Memory Sector Address High Byte Flash Memory User Programming Enable BitsFlash Memory Sector Address Low Byte Interrupt Level 2 IRQ2 Enable Bit Counter a Interrupt Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or OverflowInterrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or OverflowIPL Instruction Pointer Low Byte DBH Set1 Bank0 IPH Instruction Pointer High Byte DAH Set1 Bank0Instruction Pointer Address High Byte Instruction Pointer Address Low ByteIPR Interrupt Priority Register FFH Set1 Bank0 Not pending Pending IRQ Interrupt Request Register DCH Set1 Bank0Not pending Level 2 IRQ2 Request Pending Bit Counter a InterruptLvdcon LVD Control Register E0H Set1 Bank1 LVD Flag 2.3V Indicator BitVDD ≥ Lvdflag Level VDD Lvdflag Level P0.6/INT4 Mode Selection Bits P0.7/INT4 Mode Selection BitsP0.5/INT4 Mode Selection Bits P0.4/INT4 Mode Selection BitsP0.2/INT2 Mode Selection Bits P0.3/INT3 Mode Selection BitsP0.1/INT1 Mode Selection Bits P0.0/INT0 Mode Selection BitsP0.6 External Interrupt INT4 Enable Bit P0.7 External Interrupt INT4 Enable BitP0.5 External Interrupt INT4 Enable Bit P0.4 External Interrupt INT4 Enable BitP0.6 External Interrupt INT4 Pending Flag Bit P0.7 External Interrupt INT4 Pending Flag Bit see NoteP0.5 External Interrupt INT4 Pending Flag Bit P0.4 External Interrupt INT4 Pending Flag BitP0.6 Pull-up Resistor Enable Bit P0.7 Pull-up Resistor Enable BitP0.5 Pull-up Resistor Enable Bit P0.4 Pull-up Resistor Enable BitP1.6 Mode Selection Bits P1.7 Mode Selection BitsP1.5 Mode Selection Bits P1.4 Mode Selection BitsP1.2 Mode Selection Bits P1.3 Mode Selection BitsP1.1 Mode Selection Bits P1.0 Mode Selection BitsP2.6/INT9 Mode Selection Bits P2.7/INT9 Mode Selection BitsP2.5/INT9 Mode Selection Bits P2.4/INT9 Mode Selection BitsP2.2/INT7 Mode Selection Bits P2.3/INT8 Mode Selection BitsP2.1/INT6 Mode Selection Bits P2.0/INT5 Mode Selection BitsP2.6 External Interrupt INT9 Enable Bit P2.7 External Interrupt INT9 Enable BitP2.5 External Interrupt INT9 Enable Bit P2.4 External Interrupt INT9 Enable BitP2.6 External Interrupt INT9 Pending Flag Bit P2.7 External Interrupt INT9 Pending Flag Bit see NoteP2.5 External Interrupt INT9 Pending Flag Bit P2.4 External Interrupt INT9 Pending Flag BitP2.6 Pull-up Resistor Enable Bit P2.7 Pull-up Resistor Enable BitP2.5 Pull-up Resistor Enable Bit P2.4 Pull-up Resistor Enable BitP3CON Port 3 Control Register EFH Set1 Bank0 Each Function Description and Assignment to P3.0-P3.3 P3CONP3.4 Mode Selection Bits P3.5 Mode Selection BitsP345CON Port345 Control Register E1H Set1 Bank1 Port 4 Control Register Selection BitP4CON Port 4 Control Register F0H Set1 Bank0 P4.6 Mode Selection Bits P4.7 Mode Selection BitsP4.5 Mode Selection Bits P4.4 Mode Selection BitsP4.2 Mode Selection Bits P4.3 Mode Selection BitsP4.1 Mode Selection Bits P4.0 Mode Selection BitsDestination page 0 See Note PP Register Page Pointer DFH Set1 Bank0Source Register Page Selection Bits Source page 0 See NoteRP1 Register Pointer D7H Set1 Bank0 RP0 Register Pointer D6H Set1 Bank0Register Pointer 0 Address Value Register Pointer 1 Address ValueSPL Stack Pointer Low Byte D9H Set1 Bank0 Stop Control Register Enable BitsStopcon Stop Control Register FBH Set1 Bank0 Stack Pointer Address Low ByteFast Interrupt Enable Bit SYM System Mode Register DEH Set1 Bank0Global Interrupt Enable Bit Tri-State External Interface Control BitT0CON- Timer 0 Control Register D2H Set 1 Bank0 T1CON Timer 1 Control Register FAH Set1 Bank0 T2CON Timer 2 Control Register E8H Set1 Bank1 Vectors LevelsSources S3C8/S3F8-Series Interrupt Types Interrupt TypesS3F80JB Interrupt Structure S3F80JB Interrupt Structure ROM Vector Address Area Interrupt Vector AddressesFCH Interrupt PriorityD8H SYSTEM-LEVEL Interrupt Control Registers ENABLE/DISABLE Interrupt Instructions EI, DIInterrupt Control Register Overview Function Description Interrupt Processing Control Points Interrupt Function DiagramPeripheral Interrupt Control Registers System Mode Register SYM System Mode Register SYMInterrupt Mask Register IMR Interrupt Mask Register IMRInterrupt Request Priority Groups Interrupt Priority Register IPRInterrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQInterrupt Pending Function Types Pending Bits Cleared by the Service RoutineOverview Pending Bits Cleared Automatically by HardwareInterrupt Source Polling Sequence Interrupt Service RoutinesNesting of Vectored Interrupts Generating Interrupt Vector AddressesInstruction Pointer IP Fast Interrupt ProcessingFast Interrupt Service Routine Procedure for Initiating Fast InterruptFast Interrupt Processing Programming GuidelinesAddressing Modes Data TypesLDC LDELded LdcdLogic Instructions Bit Manipulation Instructions CPU Control Instructions System Flags Register Flags Flags Register FlagsFlag Descriptions Instruction SET Notation Instruction Set SymbolsFlag Notation Conventions Immediate long addressing mode #data data = range Immediate addressing mode #data data =@Rn or @reg reg = 0-255, n = Irr Indirect working register pair only @RRp p = 0, 2Opcode MAP Lower Nibble HEX Opcode Quick ReferenceR1,R2 R2,R1 Djnz INC NextR1,IM Djnz INC NOPCondition Codes Binary Mnemonic Description Flags Set Condition CodesInstruction Descriptions Flags ADC Add with carryFormat Bytes Cycles Dst SrcADD Add Flags Unaffected Set if the result is 0 cleared otherwise LogicalAlways cleared to Band Bit BCP BCP Bit CompareOperation Bitc Bitc Bit ComplementHex Dst Bitr dst.b Operation dstb ← Bitr Bit ResetFormat Bits dst.b Operation dstb ← Bits Bit SetBOR BOR Bit orExample Given R1 = 07H Btjrf Bit Test, Jump Relative on FalseBtjrf SKIP,R1.3 Btjrt SKIP,R1.1 Btjrt Bit Test, Jump Relative on TrueR1,01H.1 R1 = 06H, register 01H = 03H Bxor Bit XORCall Call Call Procedure@SP PCL PCH CCF CCF Complement Carry FlagOperation C ← not C Complemented No other flags are affectedCLR dst Operation dst ← CLR Clear00H Register 00H COM COM ComplementINC Skip LD CP CompareCpije Cpije Compare, Increment, and Jump on EqualCpijne Cpijne Compare, Increment, and Jump on Non-EqualIf dst src 0, PC ← PC + RA InstructionDAdst Operation dst ← DA dst DA Decimal AdjustBits R1 ← 3CH + R1,R03CH @R1 @R1 ← Leave the value 31 BCD in address 27H @R1DEC DEC DecrementDst Operation ← dst Opc Dst Examples Given R1 = 03H and register 03H = 10HDecw Decw Decrement WordOperation SYM 0 ← DI Disable InterruptsNo flags are affected Operation dst ÷ src DIV Divide UnsignedDjnz r,dst Operation r ← r Djnz Decrement and Jump if Non-ZeroJump taken No jump SRP #0C0H Djnz R1,LOOPEI Enable Interrupts Enter Enter EnterOperation SP @SP @IPExit Exit ExitOperation IP @SPIdle Idle Idle OperationINC Increment Contents of the destination operand are incremented by oneINC dst Operation dst ← dst + = 1CHIncw Incw Increment WordIncw RR0 Loop Incw RR0Iret Iret Interrupt ReturnFlags ← @SP PC ↔ IP Flags ← FlagsLabelw JP JumpExample Given The carry flag = 1 and Labelx = 1FF7H JR Jump RelativeLabelx → PC = 1FF7H Dst ← src LD Load= 0FFH, R1 = 0AH 0AHRegister 31H = 0AH, R0 = 01H, R1 = 0AH LDB LDB Load BitDst Examples Given R0 = 06H and general register 00H = 05H R0,00H.2 07H, register 00H 05HLDC/LDE Load Memory Addr ModeLDC/LDE dst,src Operation dst ← src XL L XL HExamples LDC/LDELDCD/LDED dst,src Operation dst ← src LDCD/LDED Load Memory and DecrementLDCI/LDEI dst,src Operation dst ← src LDCI/LDEI Load Memory and IncrementRr ← rr + Into R8 and RR6 is incremented by one RR6 ← RR6 +Ldcpd LDCPD/LDEPD Load Memory with Pre-DecrementOperation rr ← rr Ldcpi LDCPI/LDEPI Load Memory with Pre-IncrementOperation rr ← rr + RR IML LDW Load WordLDW RR6,RR4 Mult dst,src Mult Multiply UnsignedOperation dst ← dst ⋅ src ClearedNext Next NextOperation PC ← @ IP NOP No Operation When the instructionNOP Or Logical or POP dst Operation dst ← @SP POP Pop From Stack00H Register 00H 55H, SP = 00FCH Popud dst,src Popud Pop User Stack DecrementingPopui dst,src Popui Pop User Stack IncrementingPush src Operation SP ← SP Push Push To StackSPH = 0FFH, SPL = 0FFH 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFHPushud Pushud Push User Stack DecrementingIR ← IR Decremented stack pointerPushui dst,src Operation IR ← IR + Pushui Push User Stack IncrementingRCF RCF Reset Carry FlagFlags Cleared to RET RET ReturnOperation PC ← @SP PC = 101AH, SP = 00FEHDst 0 ← dst RL Rotate LeftDst n + 1 ← dst n, n = Set if the result bit 7 is set cleared otherwiseRLC RLC Rotate Left Through CarryRR dst RR Rotate RightOperation C ← dst Rotation cleared otherwiseRRC RRC Rotate Right Through CarryDst 7 ← C 00H Register 00H 2AH, C =SB0 SB0 Select BankOperation Bank ← StatementSB1 SB1 Select BankAlways set to SBC Subtract With CarrySet otherwise, indicating a borrow Format Bytes Cycles SCF SCF Set Carry FlagSet to No other flags are affected Sets the carry flag to logic oneSRA dst SRA Shift Right Arithmetic00H Register 00H 0CD, C = SRP SRP/SRP0/SRP1 Set Register PointerSRP0 SRP1Stop Stop Stop OperationSUB SUB SubtractSet otherwise indicating a borrow Format Bytes Cycles Swap dst Swap Swap NibblesFlags Undefined Set if the result is 0 cleared otherwise 00H Register 00H 0E3HR0,R1 = 0C7H, R1 = 02H, Z = TCM Test Complement Under MaskR0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = 00H,01H Register 00H = 2BH, register 01H = 02H, Z =TM Test Under Mask Always reset toTMdst,src Operation dst and srcWFI WFI Wait For InterruptOpc 4n 3F XOR XOR Logical Exclusive or7FH System Clock Circuit Clock CircuitsSystem Clock Circuit Diagram Clock Status During POWER-DOWN ModesSystem Clock Control Register Clkcon System Clock Control Register ClkconReset Sources ResetReset Sources of The S3F80JB EIexternal interrupt enableReset Block Diagram of The S3F80JB External Reset PIN Reset MechanismWatch DOG Timer Reset LVD ResetInternal Power-On Reset Circuit Internal POWER-ON ResetTiming Diagram for Internal Power-On Reset Circuit External Interrupt Reset Reset Timing Diagram for The S3F80JB in Stop mode by IporVreset Stop Error Detection & RecoveryReset Source Slope of V DDIdle Mode POWER-DOWN ModesIdle Mode Release Block Diagram for Back-up Mode BACK-UP ModeProgramming TIP To Enter Stop Mode Stop ModeUsing nRESET Pin to Release Stop Mode Sources to Release Stop ModeUsing Ipor to Release Stop Mode Using LVD to Release Stop ModeSED&R Stop Error Detect and Recovery System Reset Operation Dec Hardware Reset ValuesTimer 1 Data Register Low Byte Timer 1 Data Register High ByteTimer 1 Control Register Dec HexTimer 2 Data Register High Byte Timer 2 Counter Register Low ByteTimer 2 Data Register Low Byte Timer 2 Control RegisterLVD IporStop Ipor SED&R← # 0FFH Recommendation for Unusued PinsP2PUR Connect to VSSSummary of Each Mode Item/Mode Back-up Reset Status Stop Summary Table of BACK-UP MODE, Stop MODE, and Reset StatusStopcon ← # A5H LD STOPCON,#0A5HO Ports Port Configuration Options S3F80JB Port Configuration Overview 44-QFPAssigned individually as analog input pin for comparator P3.0-P3.1S3F80JB Port Configuration Overview 32-SOP S3F80JB I/O Port Data Register Format Port Data RegistersPull-up Resistor Enable Registers Port 0 and Port 2 only PULL-UP Resistor Enable RegistersTimer Basic Timer BTBasic Timer Control Register Btcon Basic Timer Control Register BtconWatch-dog Timer Function Basic Timer Function DescriptionOscillation Stabilization Interval Timer Function Timer 0 Control Register T0CON Timer 0 Control Register T0CON Timer 0 Interrupts IRQ0, Vectors FAH and FCH Timer 0 Function DescriptionInterval Timer Mode Simplified Timer 0 Function Diagram PWM Mode Pulse Width Modulation ModeSimplified Timer 0 Function Diagram Capture Mode Capture ModeBasic Timer and Timer 0 Block Diagram CLR SYM Programming TIP Configuring the Basic TimerCLR SPL Main BTCON,#52HProgramming TIP Programming Timer NO200MSSET ULT,NO200MSSET BitsT0OVER Iret Timer Timer 1 Capture Interrupt Timer 1 Overflow InterruptSimplified Timer 1 Function Diagram Interval Timer Mode Timer 1 Match InterruptTimer 1 Block Diagram Timer 1 Control Register T1CON Timer 1 Control Register T1CONTimer 1 Registers T1CNTH, T1CNTL, T1DATAH, T1DATAL Counter a Counter a Block Diagram Counter a Control Register Cacon Counter a Control Register CaconCounter a Pulse Width Calculations Method 2 When Caof =Counter a Output Flip-Flop Waveforms in Repeat Mode Through P3.1 CADATAH,# Set 40 ms Programming TIP To generate a one-pulse signal through P3.1CADATAL,# Set any value except 00H13-1 Timer 2 Capture Interrupt Timer 2 Overflow InterruptSimplified Timer 2 Function Diagram Interval Timer Mode Timer 2 Match InterruptTimer 2 Block Diagram Timer 2 Control Register T2CON Timer 2 Control Register T2CONTimer 2 Registers T2CNTH, T2CNTL, T2DATAH, T2DATAL Comparator Comparator Block Diagram for The S3F80JB Comparator Operation Conversion CharacteristicsComparator Mode Register Cmod Comparator Result Register Cmpreg Embedded Flash Memory Interface Flash ROM ConfigurationTool Program Mode User Program ModePin No Function Isptm ON-BOARD Programming Sector 15-4 ISP Sector Size ISP Reset Vector and ISP Sector SizeArea of ISP Sector ISP Sector Size BitFlash Memory User Programming Enable Register Fmusr Flash Memory Control Registers User Program ModeFlash Memory Control Register Fmcon Flash Memory Sector Address Register Fmsech Flash Memory Sector Address RegistersSector Erase Sector Configurations in User Program ModeSector Erase Flowchart in User Program Mode Sector Erase Procedure in User Program ModeProgramming TIP Sector Erase Case1. Erase one sector Btjrf FLAGS.7,NOCARRY SectoreraseNocarry Erasestart SB1 FMUSR,#0A5HProgramming Program procedure in user program modeByte Program Flowchart in a User Program Mode 10. Program Flowchart in a User Program Mode Case2. Programming in the same sector Programming TIP Programming Case1 -Byte ProgrammingLD FMSECH,#01H WRINSECTOR2Call Wrbyte WRINSECTOR50 FMSECH,#19HProgramming TIP Reading ReadingLoop LDC NZ,LOOPProgramming TIP Hard Lock Protection Hard Lock ProtectionFMCON,#01100001B LVD Flag LVDResistor String Low Voltage Detect Control Register Lvdcon LOW Voltage Detector Control Register LvdconElectrical Data 4MHz D.C. Electrical Characteristics Parameter Symbol Conditions Rating UnitParameter Symbol Conditions Min Typ Max Unit Absolute Maximum RatingsLeakage Current All output pins Output Low Leakage Current All input pins except ILIH2 and XoutVout = 0 Leakage Current All output pins Pull-Up Output LowParameter Symbol Conditions Characteristics of Low Voltage Detect CircuitData Retention Supply Voltage in Stop Mode Min Typ Max UnitTypical Low-Side Driver Sink Characteristics P3.1 only Typical High-Side Driver Source Characteristics P3.1 only Typical VDD-VOHVDD=3.3V Stop Mode Release Timing When Initiated by a Reset A.C. Electrical Characteristics 10. Input Timing for External Interrupts Port 0 and Port Oscillator Clock Circuit Conditions Min Typ Max Unit Oscillation CharacteristicsWait time TWAIT when released by an interrupt When released by a reset 216/f StabilizationOscillation Stabilization Time TA = 25 C to + 85 C, VDD = 3.6Sector Erasing Time 100 Data Access TimeChip Erasing Time VDD = 2.0 250 Number of Writing/Erasing FNwe 10,000Electrical Data 8MHZ Fosc = 8 MHz Input High Voltage TA = 25 C to + 85 C, VDD = 1.95 V to 3.6VDD = 2.35 V, IOH = 6mA VDD = 2.35 V, IOH = 2.2mA P3.0 and P2.0-2.3Leakage Current All input pins except ILIL2 Leakage Current All input pins except ILIH2Leakage Current All output pins Pull-Up Resistors VDD = 2.35 V, IOL = 12mAIdle Mode DD =3.6 MHz crystal Operating Mode DD = 3.6 MHz crystalStop Mode LVD OFF, V DD = 3.6 LVD ON, V DD = 3.6 For Back-Up Mode Low Level Detect VoltageVddv Typical VDD-VOHVDD=3.3V VDD-VOHV Typical VDD-VOHVDD=3.3VIOHmA 18-8 18-9 18-10 Parameter Symbol Condition Min Typ Max Units Comparator Electrical CharacteristicsTA = -25 C to + 85 C, VDD = 3.6 Flash Erase/Write/Read Voltage Fewrv 18-14 SOP-450A Pin SOP Package DimensionQFP-1010B Programming Socket Adapter Target BoardsTB80JB Target Board TB80JB Target Board ConfigurationJ1A Components Consisting of S3F80JB Target Board Block SymbolsVCC, GND, S IDLE, Stop LEDIdle LED JP#Stop LED Pin Connector Pin Assignment for TB80JB OTP/MTP Programmer Series In-Circuit EmulatorGW-PRO2 Development Tools SuppliersSeminix OTP/MTP Programmer Writer SPW2+GW-PRO2 Product description For what kind of product will you be using this order?Package Marking Check One Customer sample Risk orderCustomer Risk Order Agreement Risk Order InformationOrder Quantity and Delivery Schedule Delivery Date s Quantity Comments SignaturesFlash Application Notes VDD S3F80JB Important Note S3F80JB/9 is needed to nRESET pin = 0GND & Test pin = 1VDD For Serial Programming ModeS3F80JB/9 is needed to nRESET pin = 1VDD & Test pin = 0GND For Normal Operating ModeWhen nRESET pin = 1VDD & Test pin = 0GND Timing Diagram¾ When S3F80JB When Test PIN = 1VDD¾ When S3F80J9