Samsung S3F80JB manual Stop Error Detection & Recovery, Slope of V DD, Vreset, Reset Source

RESET S3F80JB

STOP ERROR DETECTION & RECOVERY

When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop or abnormal state, the falling edge input of P0 and P2.4-P2.7 generates the reset signal.

Refer to following table and figure for more information.

Table 8-1. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1” (always LVD-On)

	Condition		Reset	System Reset
			Source
Slope of VDD	VDD	The voltage level of reset pin
		(Vreset)
Rising up from	VDD ≥ VLVD	Vreset ≥ VIH	LVD circuit	System reset occurs
VDD < VLVD
	VDD ≥ VLVD	Vreset < VIH	–	No system reset
	VDD < VLVD	Transition from	–	No system reset
		“Vreset < VIL” to “VIH < Vreset”
Standstill	VDD ≥ VLVD	Transition from	Reset pin	System reset occurs
(VDD ≥ VLVD)		“Vreset < VIL” to “VIH < Vreset”

Table 8-2. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0”

Condition

Slope of VDD	VDD	The voltage level of reset pin
		(Vreset)
Rising up from	VDD ≥ VLVD	Vreset ≥ VIH
0.4 VDD < VDD <
	VDD > VLVD	Vreset < VIH
VLVD
	VDD < VLVD	Transition from
		“Vreset < VIL” to “VIH < Vreset”
Rising up from	VDD ≥ VLVD	Vreset ≥ VIH
VDD < 0.4VDD
	VDD > VLVD	Vreset < VIH
	VDD < VLVD	Transition from
		“Vreset < VIL” to “VIH < Vreset”
Standstill	VDD ≥ VLVD	Transition from
(VDD ≥ VLVD)		“Vreset < VIL” to “VIH < Vreset”

Reset

Source

–

–

–

Internal POR

–

–

Reset pin

System Reset

No system reset

No system reset

No system reset

System reset occurs

No system reset

No system reset

System reset occurs

NOTE: IPOR / LVD control bit is included in smart option at address 003FH. (3FH.7)

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