Samsung S3F80JB manual Timer 2 Overflow Interrupt, Timer 2 Capture Interrupt

TIMER 2 S3F80JB

TIMER 2 OVERFLOW INTERRUPT

Timer 2 can be programmed to generate an overflow interrupt (IRQ3, F0H) whenever an overflow occurs in the

16-bit up counter. When you set the timer 2 overflow interrupt enable bit, T2CON.2, to “1”, the overflow interrupt is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T2CON.3, you can clear/reset the 16-bit counter value at any time during program operation.

TIMER 2 CAPTURE INTERRUPT

Timer 2 can be used to generate a capture interrupt (IRQ3, vector F2H) whenever a triggering condition is detected at the P3.0 pin for 32 pin package and P3.3 pin for 44 pin package. The T2CON.5 and T2CON.4 bit-pair setting is used to select the trigger condition for capture mode operation: rising edges, falling edges, or both signal edges.

In capture mode, program software can poll the timer 2 match/capture interrupt pending bit, T2CON.0, to detect when a timer 2 capture interrupt pending condition exists (T2CON.0 = “1”). When the interrupt request is acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F2H must clear the interrupt pending condition by writing a “0” to T2CON.0.

T2CON.2

CLK 16-Bit Up Counter

IRQ3 (T2OVF)

P3.0 or P3.3

(note)

T2CON.5

T2CON.4

Timer 2 Data

Pending

(T2CON.0)

Interrupt Enable/Disable (T2CON.1)

IRQ3 (T2INT)

NOTE: P3.0 is assigned as T2CAP function for 32 pin package and P3.3 is assigned as T2CAP function for 42/44 pin package.

Figure 13-1. Simplified Timer 2 Function Diagram: Capture Mode

13-2