Samsung S3F80JB manual Peripheral Interrupt Control Registers

S3F80JB INTERRUPT STRUCTURE

PERIPHERAL INTERRUPT CONTROL REGISTERS

For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral (See Table 5-3).

Table 5-3. Vectored Interrupt Source Control and Data Registers

Interrupt Source	Interrupt Level	Register(s)	Location(s) in Set 1	Bank
Timer 0 match/capture or	IRQ0	T0CON (see Note)	D2H	Bank0
Timer 0 overflow		T0DATA	D1H
Timer 1 match/capture or	IRQ1	T1CON (see Note)	FAH	Bank0
Timer 1 overflow		T1DATAH, T1DATAL	F8H, F9H
Counter A	IRQ2	CACON	F3H	Bank0
		CADATAH, CADATAL	F4H, F5H
Timer 2 match/capture or	IRQ3	T2CON (see Note)	E8H	Bank1
Timer 2 overflow		T2DATAH, T2DATAL	E6H, E7H
P0.7 external interrupt	IRQ7	P0CONH	E8H	Bank0
P0.6 external interrupt		P0INT	F1H
P0.5 external interrupt		P0PND	F2H
P0.4 external interrupt
P0.3 external interrupt	IRQ6	P0CONL	E9H	Bank0
P0.2 external interrupt		P0INT	F1H
P0.1 external interrupt		P0PND	F2H
P0.0 external interrupt
P2.7 external interrupt	IRQ5	P2CONH	ECH	Bank0
P2.6 external interrupt		P2INT	E5H
P2.5 external interrupt		P2PND	E6H
P2.4 external interrupt
P2.3 external interrupt	IRQ4	P2CONL	EDH	Bank0
P2.2 external interrupt		P2INT	E5H
P2.1 external interrupt		P2PND	E6H
P2.0 external interrupt

NOTES:

1.Because the timer 0,timer1 and timer 2 overflow interrupts are cleared by hardware, the T0CON, T1CON and T2CON registers control only the enable/disable functions. The T0CON, T1CON and T2CON registers contain enable/disable and pending bits for the timer 0, timer1 and timer2 match/capture interrupts, respectively.

2.If a interrupt is un-mask(Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt should be written after a DI instruction is executed.

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