Samsung S3F80JB manual Basic Timer and Timer 0 Block Diagram

S3F80JB BASIC TIMER and TIMER 0

Bit 1

RESET or STOP

Bits 3, 2

Data Bus

Basic Timer Control Register

(Write '1010xxxxB' to disable.)

1/4096

Clear

XIN

DIV

1/1024

MUX

8-Bit Up Counter

OVF

RESET

(BTCNT, Read-Only)

1/128

R

When BTCNT.4 is set after releasing from

RESET or STOP mode, CPU clock starts.

Bit 0

Bits 7, 6

Bit 2

Data Bus

OVF

IRQ0

1/4096

R

(Timer 0 Overflow)

1/256

8-Bit Up-Counter R

XIN

DIV

1/8

MUX

Clear

Bit 3

(T0CNT)

P3.1/T0CK			Match (2)	Bit 1
or
P3.2/T0CK	GND	8-Bit Compatator		Bit 0	IRQ0
(note 3)
					(Timer 0 Match)
P3.0/T0CAP				T0PWM
		Timer 0 Buffer
		Register	Bits 5, 4
	Bits 5, 4		Match Signal
			T0CON.3
			T0OVF

Timer 0 Data Register

(T0DATA)

Basic Timer Control Register

Data Bus Timer 0 Control Register

NOTES:

1.During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).

2.It is available only in using internal mode.

3.The external clock source is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 42/44-pin package.

Figure 10-7. Basic Timer and Timer 0 Block Diagram

10-9