Samsung S3F80JB manual Counter a Control Register Cacon

S3F80JB COUNTER A

COUNTER A CONTROL REGISTER (CACON)

The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON contains control settings for the following functions (See Figure 12-2):

—Counter A clock source selection

—Counter A interrupt enable/disable

—Counter A interrupt pending control (read for status, write to clear)

—Counter A interrupt time selection

Counter A Control Register (CACON)

F3H, Set 1, Bank 0, R/W

	MSB	.7	.6	.5	.4	.3	.2	.1		.0		LSB
									Counter		A Output Flip-Flop Control Bit(CAOF):
Counter A Input Clock Selection Bits:
00	= fOSC								0 = T-F/F is low
01	= fOSC/2								1 = T-F/F is high
10	= fOSC/4							Counter A Mode Selection Bit:
11	= fOSC/8
								0 = One shot mode
Counter A Interrupt Time Selection Bits:								1 = Repeating mode
00	= Elapsed time for low data value
							Counter A Start/Stop Bit:
01	= Elapsed time for high data value
							0 = Stop counter A
10	= Elapsed time for low and high data values
							1 = Start counter A
11	= Invalid setting

Counter A Interrupt Enable Bit: 0 = Disable interrupt

1 = Enable interrupt

Figure 12-2. Counter A Control Register (CACON)

Counter A Data High-Byte Register (CADATAH)

F4H, Set 1, Bank 0, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0 LSB

Reset Value: FFH

Counter A Data Low-Byte Register (CADATAL)

F5H, Set 1, Bank 0, R/W

MSB .7

.6

.5

.4

.3

.2

.1

.0 LSB

Reset Value: FFH

Figure 12-3. Counter A Registers

12-3