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Samsung manual EIexternal interrupt enable, Reset Sources of The S3F80JB

Models: S3F80JB

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RESET	S3F80JB

STOP

IPOR / LVD Contorl Bit '1'

(smart option bit[7] @03FH)

LVD

IPOR / LVD Contorl Bit '1' (smart option bit[7] @03FH)

STOP

IPOR
Watchdog Timer	1
	2
	3	RESET
nRESET	4	RESET
nRESET	5
	5
	6

P0&P2 (INT0-INT9)

(EI)external interrupt enable

(smart option bit[7] @03FH) IPOR / LVD Contorl Bit '1'

STOP

P0 & P2.4-2.7

(smart option bit[7] @03FH) IPOR / LVD Contorl Bit '1'

STOP

Figure 8-1. RESET Sources of The S3F80JB

1.When IPOR/LVD Control Bit of smart option is set to ‘1’, the rising edge detection of LVD circuit while rising of VDD passes the level of VLVD.

2.When IPOR/LVD Control Bit of smart option is set to ‘0’ and mode is in STOP Mode, reset is generated by internal power-on reset.

3.Basic Timer over-flow for watchdog timer. See the chapter 11. Basic Timer and Timer 0 for more understanding.

4.The reset pulse generation by transiting of reset pin (nRESET) from low level to high level on the condition that VDD is higher level state than VLVD (Low level Detect Voltage).

5.When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’ and chip is in stop mode, external interrupt input by P0 and P2 regardless of external interrupt enable/disable generates the reset signal.

8-2

Image 220

Samsung manual EIexternal interrupt enable, Reset Sources of The S3F80JB

Contents

S3F80JB Important Notice Reset Part Programming ModelTable of Contents Interrupt Structure Reset Summary Table of Back-Up Mode, Stop Mode, and Reset StatusTimer 10-110-2 10-3Flash Memory User Programming Enable Register Fmusr 15-6 15-115-3 15-5List of Figures Title Number10-5 10-710-8 10-917-3 Typical Low-Side Driver Sink Characteristics 17-6 Typical High-Side Driver Source Characteristics12-2 12-518-3 Typical Low-Side Driver Sink Characteristics 18-6 Typical High-Side Driver Source Characteristics18-2 18-4Reset Condition in Stop Mode When Ipor / LVD Control Bit is List of Tables17-3 17-617-13 18-3Chapter Reset Chapter Basic Timer and TimerDescription Chapter Address SpacesRegister Full Register Name Identifier Instruction Full Register Name Mnemonic Next NOPPOP PopudS3C8/S3F8-SERIES Microcontrollers S3F80JB MicrocontrollerFeatures CPUBlock Diagram 32-PIN Package Block Diagram 32-pinBlock Diagram 44-PIN Package Block Diagram 44-pinPin Assignment Diagram 32-Pin SOP Package PIN AssignmentsS3F80JB PIN Assignments44-QFP Pin Descriptions of 32-SOP Circuit 32 Pin Shared Names Pin Descriptions of 44-QFP Circuit 44 Pin Shared Names P3.1 Port with bit-programmable pin. Configurable to PIN Circuits Pin Circuit Type 1 Port 0 and Port2PIN Circuits Pin Circuit Type 2 Port 1, Port4, P3.4 and P3.5Pin Circuit Type 3 P3.0 Pin Circuit Type 4 P3.1 10. Pin Circuit Type 6 nRESET Address Space OverviewProgram Memory Program Memory Address SpaceSmart Option Smart OptionS3F80JB Address Spaces Summary of S3F80JB Register Type Number of Bytes Register ArchitectureTotal Addressable Bytes 333 Internal Register File Organization Register page Pointer PP Register Page Pointer PPRegister SET Prime Register Space Set 1, Set 2, and Prime Area Register MapWorking Registers Byte Working Register Areas SlicesUsing the Register Pointers Programming TIP Setting the Register Pointers#80H RP0 ← 80H R0,R1 ← R0 +R0,R2 R0,R3Register Addressing Bit Register Pair10. Register File Addressing Common Working Register Area C0H-CFH RP1 → C8H-CFHExample Programming TIP Addressing the Common Working Register AreaBIT Working Register Addressing 12 -Bit Working Register Addressing 14 -Bit Working Register Addressing 15 -Bit Working Register Addressing Example Stack Operations System and User StacksStack Pointers SPL SPL,#0FFH SPL ← FFH Push RP0Push RP1 POP RP1Addressing Modes Register Addressing Mode R Register AddressingIndirect Register Addressing Mode IR Indirect Register Addressing to Register FileIndirect Register Addressing Mode Indirect Register Addressing to Program MemoryIndirect Working Register Addressing to Register File LCD Indexed Addressing Mode Indexed Addressing to Register FileIndexed Addressing Mode Next 2 BitsIndexed Addressing to Program or Data Memory Direct Address Mode DA 10. Direct Addressing for Load InstructionsDirect Address Mode 11. Direct Addressing for Call and Jump InstructionsIndirect Address Mode IA 12. Indirect AddressingRelative Address Mode RA 13. Relative AddressingImmediate Mode IM 14. Immediate AddressingControl Registers T0CNT D0HT0DATA D1HMapped Registers Register Name Mnemonic Decimal Hex Register Description Format Btcon Basic Timer Control Register D3H Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing ModeWatchdog Timer Function Enable Bits for System Reset Basic Timer Input Clock Selection BitsCacon Counter a Control Register F3H Set1 Bank0 CPU Clock System Clock Selection Bits Clkcon System Clock Control Register D4H Set1 Bank0Subsystem Clock Selection Bits Cmod Comparator Mode Register E9H Set1 Bank1 Comparator Enable BitConversion Timer Control Bit External Reference Selection BitCmpsel Comparator Input Selection Register EBH Set1 Bank1 P2.7 Function Selection BitP2.6 Function Selection Bit P2.5 Function Selection BitEMT External Memory Timing Register Note FEH Set1 Bank0 Flags System Flags Register D5H Set1 Bank0 Fmcon Flash Memory Control Register EFH Set1 Bank1 Flash Memory Mode Selection BitsOperation stop Operation start auto clear bit Flash Memory Sector Address High Byte Flash Memory User Programming Enable BitsFlash Memory Sector Address Low Byte Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or Overflow Interrupt Level 2 IRQ2 Enable Bit Counter a InterruptInterrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or OverflowIPH Instruction Pointer High Byte DAH Set1 Bank0 IPL Instruction Pointer Low Byte DBH Set1 Bank0Instruction Pointer Address High Byte Instruction Pointer Address Low ByteIPR Interrupt Priority Register FFH Set1 Bank0 IRQ Interrupt Request Register DCH Set1 Bank0 Not pending PendingNot pending Level 2 IRQ2 Request Pending Bit Counter a InterruptLvdcon LVD Control Register E0H Set1 Bank1 LVD Flag 2.3V Indicator BitVDD ≥ Lvdflag Level VDD Lvdflag Level P0.7/INT4 Mode Selection Bits P0.6/INT4 Mode Selection BitsP0.5/INT4 Mode Selection Bits P0.4/INT4 Mode Selection BitsP0.3/INT3 Mode Selection Bits P0.2/INT2 Mode Selection BitsP0.1/INT1 Mode Selection Bits P0.0/INT0 Mode Selection BitsP0.7 External Interrupt INT4 Enable Bit P0.6 External Interrupt INT4 Enable BitP0.5 External Interrupt INT4 Enable Bit P0.4 External Interrupt INT4 Enable BitP0.7 External Interrupt INT4 Pending Flag Bit see Note P0.6 External Interrupt INT4 Pending Flag BitP0.5 External Interrupt INT4 Pending Flag Bit P0.4 External Interrupt INT4 Pending Flag BitP0.7 Pull-up Resistor Enable Bit P0.6 Pull-up Resistor Enable BitP0.5 Pull-up Resistor Enable Bit P0.4 Pull-up Resistor Enable BitP1.7 Mode Selection Bits P1.6 Mode Selection BitsP1.5 Mode Selection Bits P1.4 Mode Selection BitsP1.3 Mode Selection Bits P1.2 Mode Selection BitsP1.1 Mode Selection Bits P1.0 Mode Selection BitsP2.7/INT9 Mode Selection Bits P2.6/INT9 Mode Selection BitsP2.5/INT9 Mode Selection Bits P2.4/INT9 Mode Selection BitsP2.3/INT8 Mode Selection Bits P2.2/INT7 Mode Selection BitsP2.1/INT6 Mode Selection Bits P2.0/INT5 Mode Selection BitsP2.7 External Interrupt INT9 Enable Bit P2.6 External Interrupt INT9 Enable BitP2.5 External Interrupt INT9 Enable Bit P2.4 External Interrupt INT9 Enable BitP2.7 External Interrupt INT9 Pending Flag Bit see Note P2.6 External Interrupt INT9 Pending Flag BitP2.5 External Interrupt INT9 Pending Flag Bit P2.4 External Interrupt INT9 Pending Flag BitP2.7 Pull-up Resistor Enable Bit P2.6 Pull-up Resistor Enable BitP2.5 Pull-up Resistor Enable Bit P2.4 Pull-up Resistor Enable BitP3CON Port 3 Control Register EFH Set1 Bank0 P3CON Each Function Description and Assignment to P3.0-P3.3P3.5 Mode Selection Bits P3.4 Mode Selection BitsP345CON Port345 Control Register E1H Set1 Bank1 Port 4 Control Register Selection BitP4CON Port 4 Control Register F0H Set1 Bank0 P4.7 Mode Selection Bits P4.6 Mode Selection BitsP4.5 Mode Selection Bits P4.4 Mode Selection BitsP4.3 Mode Selection Bits P4.2 Mode Selection BitsP4.1 Mode Selection Bits P4.0 Mode Selection BitsPP Register Page Pointer DFH Set1 Bank0 Destination page 0 See NoteSource Register Page Selection Bits Source page 0 See NoteRP0 Register Pointer D6H Set1 Bank0 RP1 Register Pointer D7H Set1 Bank0Register Pointer 0 Address Value Register Pointer 1 Address ValueStop Control Register Enable Bits SPL Stack Pointer Low Byte D9H Set1 Bank0Stopcon Stop Control Register FBH Set1 Bank0 Stack Pointer Address Low ByteSYM System Mode Register DEH Set1 Bank0 Fast Interrupt Enable BitGlobal Interrupt Enable Bit Tri-State External Interface Control BitT0CON- Timer 0 Control Register D2H Set 1 Bank0 T1CON Timer 1 Control Register FAH Set1 Bank0 T2CON Timer 2 Control Register E8H Set1 Bank1 Vectors LevelsSources Interrupt Types S3C8/S3F8-Series Interrupt TypesS3F80JB Interrupt Structure S3F80JB Interrupt Structure Interrupt Vector Addresses ROM Vector Address AreaFCH Interrupt PriorityD8H SYSTEM-LEVEL Interrupt Control Registers ENABLE/DISABLE Interrupt Instructions EI, DIInterrupt Control Register Overview Function Description Interrupt Function Diagram Interrupt Processing Control PointsPeripheral Interrupt Control Registers System Mode Register SYM System Mode Register SYMInterrupt Mask Register IMR Interrupt Mask Register IMRInterrupt Priority Register IPR Interrupt Request Priority GroupsInterrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQPending Bits Cleared by the Service Routine Interrupt Pending Function TypesOverview Pending Bits Cleared Automatically by HardwareInterrupt Service Routines Interrupt Source Polling SequenceGenerating Interrupt Vector Addresses Nesting of Vectored InterruptsInstruction Pointer IP Fast Interrupt ProcessingProcedure for Initiating Fast Interrupt Fast Interrupt Service RoutineFast Interrupt Processing Programming GuidelinesData Types Addressing ModesLDE LDCLded LdcdLogic Instructions Bit Manipulation Instructions CPU Control Instructions Flags Register Flags System Flags Register FlagsFlag Descriptions Instruction SET Notation Instruction Set SymbolsFlag Notation Conventions Immediate addressing mode #data data = Immediate long addressing mode #data data = range@Rn or @reg reg = 0-255, n = Irr Indirect working register pair only @RRp p = 0, 2Opcode Quick Reference Opcode MAP Lower Nibble HEXDjnz INC Next R1,R2 R2,R1R1,IM Djnz INC NOPCondition Codes Condition Codes Binary Mnemonic Description Flags SetInstruction Descriptions ADC Add with carry FlagsFormat Bytes Cycles Dst SrcADD Add Flags Unaffected Set if the result is 0 cleared otherwise LogicalAlways cleared to Band Bit BCP BCP Bit CompareOperation Bitc Bitc Bit ComplementHex Dst Bitr dst.b Operation dstb ← Bitr Bit ResetFormat Bits Bit Set Bits dst.b Operation dstb ←BOR Bit or BORExample Given R1 = 07H Btjrf Bit Test, Jump Relative on FalseBtjrf SKIP,R1.3 Btjrt Bit Test, Jump Relative on True Btjrt SKIP,R1.1Bxor Bit XOR R1,01H.1 R1 = 06H, register 01H = 03HCall Call Call Procedure@SP PCL PCH CCF Complement Carry Flag CCFOperation C ← not C Complemented No other flags are affectedCLR dst Operation dst ← CLR Clear00H Register 00H COM Complement COMCP Compare INC Skip LDCpije Compare, Increment, and Jump on Equal CpijeCpijne Compare, Increment, and Jump on Non-Equal CpijneIf dst src 0, PC ← PC + RA InstructionDAdst Operation dst ← DA dst DA Decimal AdjustBits R1,R0 R1 ← 3CH +3CH @R1 @R1 ← Leave the value 31 BCD in address 27H @R1DEC Decrement DECDst Operation ← dst Opc Dst Examples Given R1 = 03H and register 03H = 10HDecw Decrement Word DecwOperation SYM 0 ← DI Disable InterruptsNo flags are affected DIV Divide Unsigned Operation dst ÷ srcDjnz Decrement and Jump if Non-Zero Djnz r,dst Operation r ← rJump taken No jump SRP #0C0H Djnz R1,LOOPEI Enable Interrupts Enter Enter EnterOperation SP @SP @IPExit Exit ExitOperation IP @SPIdle Idle Operation IdleContents of the destination operand are incremented by one INC IncrementINC dst Operation dst ← dst + = 1CHIncw Increment Word IncwIncw RR0 Loop Incw RR0Iret Interrupt Return IretFlags ← @SP PC ↔ IP Flags ← FlagsJP Jump LabelwExample Given The carry flag = 1 and Labelx = 1FF7H JR Jump RelativeLabelx → PC = 1FF7H LD Load Dst ← src= 0FFH, R1 = 0AH 0AHRegister 31H = 0AH, R0 = 01H, R1 = 0AH LDB Load Bit LDBDst Examples Given R0 = 06H and general register 00H = 05H R0,00H.2 07H, register 00H 05HAddr Mode LDC/LDE Load MemoryLDC/LDE dst,src Operation dst ← src XL L XL HLDC/LDE ExamplesLDCD/LDED Load Memory and Decrement LDCD/LDED dst,src Operation dst ← srcLDCI/LDEI Load Memory and Increment LDCI/LDEI dst,src Operation dst ← srcRr ← rr + Into R8 and RR6 is incremented by one RR6 ← RR6 +Ldcpd LDCPD/LDEPD Load Memory with Pre-DecrementOperation rr ← rr Ldcpi LDCPI/LDEPI Load Memory with Pre-IncrementOperation rr ← rr + RR IML LDW Load WordLDW RR6,RR4 Mult Multiply Unsigned Mult dst,srcOperation dst ← dst ⋅ src ClearedNext Next NextOperation PC ← @ IP NOP No Operation When the instructionNOP Or Logical or POP dst Operation dst ← @SP POP Pop From Stack00H Register 00H 55H, SP = 00FCH Popud Pop User Stack Decrementing Popud dst,srcPopui Pop User Stack Incrementing Popui dst,srcPush Push To Stack Push src Operation SP ← SPSPH = 0FFH, SPL = 0FFH 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFHPushud Push User Stack Decrementing PushudIR ← IR Decremented stack pointerPushui Push User Stack Incrementing Pushui dst,src Operation IR ← IR +RCF RCF Reset Carry FlagFlags Cleared to RET Return RETOperation PC ← @SP PC = 101AH, SP = 00FEHRL Rotate Left Dst 0 ← dstDst n + 1 ← dst n, n = Set if the result bit 7 is set cleared otherwiseRLC Rotate Left Through Carry RLCRR Rotate Right RR dstOperation C ← dst Rotation cleared otherwiseRRC Rotate Right Through Carry RRCDst 7 ← C 00H Register 00H 2AH, C =SB0 Select Bank SB0Operation Bank ← StatementSB1 Select Bank SB1Always set to SBC Subtract With CarrySet otherwise, indicating a borrow Format Bytes Cycles SCF Set Carry Flag SCFSet to No other flags are affected Sets the carry flag to logic oneSRA dst SRA Shift Right Arithmetic00H Register 00H 0CD, C = SRP/SRP0/SRP1 Set Register Pointer SRPSRP0 SRP1Stop Stop Operation StopSUB SUB SubtractSet otherwise indicating a borrow Format Bytes Cycles Swap Swap Nibbles Swap dstFlags Undefined Set if the result is 0 cleared otherwise 00H Register 00H 0E3HTCM Test Complement Under Mask R0,R1 = 0C7H, R1 = 02H, Z =R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = 00H,01H Register 00H = 2BH, register 01H = 02H, Z =Always reset to TM Test Under MaskTMdst,src Operation dst and srcWFI WFI Wait For InterruptOpc 4n 3F XOR XOR Logical Exclusive or7FH Clock Circuits System Clock CircuitClock Status During POWER-DOWN Modes System Clock Circuit DiagramSystem Clock Control Register Clkcon System Clock Control Register ClkconReset Reset SourcesEIexternal interrupt enable Reset Sources of The S3F80JBReset Block Diagram of The S3F80JB Reset Mechanism External Reset PINWatch DOG Timer Reset LVD ResetInternal POWER-ON Reset Internal Power-On Reset CircuitTiming Diagram for Internal Power-On Reset Circuit Reset Timing Diagram for The S3F80JB in Stop mode by Ipor External Interrupt ResetStop Error Detection & Recovery VresetReset Source Slope of V DDIdle Mode POWER-DOWN ModesIdle Mode Release BACK-UP Mode Block Diagram for Back-up ModeStop Mode Programming TIP To Enter Stop ModeSources to Release Stop Mode Using nRESET Pin to Release Stop ModeUsing Ipor to Release Stop Mode Using LVD to Release Stop ModeSED&R Stop Error Detect and Recovery System Reset Operation Hardware Reset Values DecTimer 1 Data Register High Byte Timer 1 Data Register Low ByteTimer 1 Control Register Dec HexTimer 2 Counter Register Low Byte Timer 2 Data Register High ByteTimer 2 Data Register Low Byte Timer 2 Control RegisterIpor LVDStop Ipor SED&RRecommendation for Unusued Pins ← # 0FFHP2PUR Connect to VSSSummary Table of BACK-UP MODE, Stop MODE, and Reset Status Summary of Each Mode Item/Mode Back-up Reset Status StopStopcon ← # A5H LD STOPCON,#0A5HO Ports S3F80JB Port Configuration Overview 44-QFP Port Configuration OptionsAssigned individually as analog input pin for comparator P3.0-P3.1S3F80JB Port Configuration Overview 32-SOP Port Data Registers S3F80JB I/O Port Data Register FormatPULL-UP Resistor Enable Registers Pull-up Resistor Enable Registers Port 0 and Port 2 onlyBasic Timer BT TimerBasic Timer Control Register Btcon Basic Timer Control Register BtconWatch-dog Timer Function Basic Timer Function DescriptionOscillation Stabilization Interval Timer Function Timer 0 Control Register T0CON Timer 0 Control Register T0CON Timer 0 Interrupts IRQ0, Vectors FAH and FCH Timer 0 Function DescriptionInterval Timer Mode Pulse Width Modulation Mode Simplified Timer 0 Function Diagram PWM ModeCapture Mode Simplified Timer 0 Function Diagram Capture ModeBasic Timer and Timer 0 Block Diagram Programming TIP Configuring the Basic Timer CLR SYMCLR SPL Main BTCON,#52HProgramming TIP Programming Timer NO200MSSET ULT,NO200MSSET BitsT0OVER Iret Timer Timer 1 Overflow Interrupt Timer 1 Capture InterruptTimer 1 Match Interrupt Simplified Timer 1 Function Diagram Interval Timer ModeTimer 1 Block Diagram Timer 1 Control Register T1CON Timer 1 Control Register T1CONTimer 1 Registers T1CNTH, T1CNTL, T1DATAH, T1DATAL Counter a Counter a Block Diagram Counter a Control Register Cacon Counter a Control Register CaconMethod 2 When Caof = Counter a Pulse Width CalculationsCounter a Output Flip-Flop Waveforms in Repeat Mode Through P3.1 Programming TIP To generate a one-pulse signal through P3.1 CADATAH,# Set 40 msCADATAL,# Set any value except 00H13-1 Timer 2 Overflow Interrupt Timer 2 Capture InterruptTimer 2 Match Interrupt Simplified Timer 2 Function Diagram Interval Timer ModeTimer 2 Block Diagram Timer 2 Control Register T2CON Timer 2 Control Register T2CONTimer 2 Registers T2CNTH, T2CNTL, T2DATAH, T2DATAL Comparator Comparator Block Diagram for The S3F80JB Conversion Characteristics Comparator OperationComparator Mode Register Cmod Comparator Result Register Cmpreg Flash ROM Configuration Embedded Flash Memory InterfaceTool Program Mode User Program ModePin No Function Isptm ON-BOARD Programming Sector 15-4 ISP Reset Vector and ISP Sector Size ISP Sector SizeArea of ISP Sector ISP Sector Size BitFlash Memory User Programming Enable Register Fmusr Flash Memory Control Registers User Program ModeFlash Memory Control Register Fmcon Flash Memory Sector Address Registers Flash Memory Sector Address Register FmsechSector Configurations in User Program Mode Sector EraseSector Erase Procedure in User Program Mode Sector Erase Flowchart in User Program ModeProgramming TIP Sector Erase Case1. Erase one sector Sectorerase Btjrf FLAGS.7,NOCARRYNocarry Erasestart SB1 FMUSR,#0A5HProgram procedure in user program mode ProgrammingByte Program Flowchart in a User Program Mode 10. Program Flowchart in a User Program Mode Programming TIP Programming Case1 -Byte Programming Case2. Programming in the same sectorWRINSECTOR2 LD FMSECH,#01HCall Wrbyte WRINSECTOR50 FMSECH,#19HReading Programming TIP ReadingLoop LDC NZ,LOOPProgramming TIP Hard Lock Protection Hard Lock ProtectionFMCON,#01100001B LVD LVD FlagResistor String LOW Voltage Detector Control Register Lvdcon Low Voltage Detect Control Register LvdconElectrical Data 4MHz Parameter Symbol Conditions Rating Unit D.C. Electrical CharacteristicsParameter Symbol Conditions Min Typ Max Unit Absolute Maximum RatingsLeakage Current All input pins except ILIH2 and Xout Leakage Current All output pins Output LowVout = 0 Leakage Current All output pins Pull-Up Output LowCharacteristics of Low Voltage Detect Circuit Parameter Symbol ConditionsData Retention Supply Voltage in Stop Mode Min Typ Max UnitTypical Low-Side Driver Sink Characteristics P3.1 only Typical High-Side Driver Source Characteristics P3.1 only Typical VDD-VOHVDD=3.3V Stop Mode Release Timing When Initiated by a Reset A.C. Electrical Characteristics 10. Input Timing for External Interrupts Port 0 and Port Oscillation Characteristics Oscillator Clock Circuit Conditions Min Typ Max UnitWhen released by a reset 216/f Stabilization Wait time TWAIT when released by an interruptOscillation Stabilization Time TA = 25 C to + 85 C, VDD = 3.6100 Data Access Time Sector Erasing TimeChip Erasing Time VDD = 2.0 250 Number of Writing/Erasing FNwe 10,000Electrical Data 8MHZ TA = 25 C to + 85 C, VDD = 1.95 V to 3.6 Fosc = 8 MHz Input High VoltageVDD = 2.35 V, IOH = 6mA VDD = 2.35 V, IOH = 2.2mA P3.0 and P2.0-2.3Leakage Current All input pins except ILIH2 Leakage Current All input pins except ILIL2Leakage Current All output pins Pull-Up Resistors VDD = 2.35 V, IOL = 12mAOperating Mode DD = 3.6 MHz crystal Idle Mode DD =3.6 MHz crystalStop Mode LVD OFF, V DD = 3.6 LVD ON, V DD = 3.6 For Back-Up Mode Low Level Detect VoltageVddv Typical VDD-VOHVDD=3.3V VDD-VOHV Typical VDD-VOHVDD=3.3VIOHmA 18-8 18-9 18-10 Comparator Electrical Characteristics Parameter Symbol Condition Min Typ Max UnitsTA = -25 C to + 85 C, VDD = 3.6 Flash Erase/Write/Read Voltage Fewrv 18-14 Pin SOP Package Dimension SOP-450AQFP-1010B Target Boards Programming Socket AdapterTB80JB Target Board Configuration TB80JB Target BoardComponents Consisting of S3F80JB Target Board Block Symbols J1AVCC, GND, S IDLE, Stop LEDIdle LED JP#Stop LED Pin Connector Pin Assignment for TB80JB Series In-Circuit Emulator OTP/MTP ProgrammerGW-PRO2 Development Tools SuppliersSeminix OTP/MTP Programmer Writer SPW2+GW-PRO2 For what kind of product will you be using this order? Product descriptionPackage Marking Check One Customer sample Risk orderRisk Order Information Customer Risk Order AgreementOrder Quantity and Delivery Schedule Delivery Date s Quantity Comments SignaturesFlash Application Notes VDD S3F80JB Important Note For Serial Programming Mode S3F80JB/9 is needed to nRESET pin = 0GND & Test pin = 1VDDFor Normal Operating Mode S3F80JB/9 is needed to nRESET pin = 1VDD & Test pin = 0GNDWhen nRESET pin = 1VDD & Test pin = 0GND Timing DiagramWhen Test PIN = 1VDD ¾ When S3F80JB¾ When S3F80J9