LDCPD/LDEPD Load Memory with Pre-Decrement, Ldcpd | Samsung S3F80JB

INSTRUCTION SET	S3F80JB

LDCPD/LDEPD — Load Memory with Pre-Decrement

LDCPD/

LDEPD dst,src

Operation: rr ← rr – 1

dst ← src

These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected.

LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory.

Flags: No flags are affected.

Format:

opc

src dst

Bytes	Cycles	Opcode	Addr Mode
		(Hex)	dst	src
2	14	F2	Irr	r

Examples: Given: R0 = 77H, R6 = 30H, and R7 = 00H:

LDCPD	@RR6,R0	;	(RR6 ← RR6 – 1)
		; 77H (contents of R0) is loaded into program memory location
		; 2FFFH (3000H – 1H)
		;	R0 = 77H, R6 = 2FH, R7 = 0FFH
LDEPD	@RR6,R0	;	(RR6 ← RR6 – 1)
		; 77H (contents of R0) is loaded into external data memory
		; location 2FFFH (3000H – 1H)
		;	R0 = 77H, R6 = 2FH, R7 = 0FFH

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Samsung S3F80JB manual LDCPD/LDEPD Load Memory with Pre-Decrement, Ldcpd, Operation rr ← rr

Contents

S3F80JB Important Notice Reset Part Programming Model Table of Contents Interrupt Structure Reset Summary Table of Back-Up Mode, Stop Mode, and Reset Status Timer 10-110-2 10-3 Flash Memory User Programming Enable Register Fmusr 15-6 15-115-3 15-5 List of Figures Title Number 10-5 10-710-8 10-9 17-3 Typical Low-Side Driver Sink Characteristics 17-6 Typical High-Side Driver Source Characteristics12-2 12-5 18-3 Typical Low-Side Driver Sink Characteristics 18-6 Typical High-Side Driver Source Characteristics18-2 18-4 Reset Condition in Stop Mode When Ipor / LVD Control Bit is List of Tables 17-3 17-617-13 18-3 Chapter Reset Chapter Basic Timer and TimerDescription Chapter Address Spaces Register Full Register Name Identifier Instruction Full Register Name Mnemonic Next NOPPOP Popud S3C8/S3F8-SERIES Microcontrollers S3F80JB Microcontroller Features CPU Block Diagram 32-PIN Package Block Diagram 32-pin Block Diagram 44-PIN Package Block Diagram 44-pin Pin Assignment Diagram 32-Pin SOP Package PIN Assignments S3F80JB PIN Assignments44-QFP Pin Descriptions of 32-SOP Circuit 32 Pin Shared Names Pin Descriptions of 44-QFP Circuit 44 Pin Shared Names P3.1 Port with bit-programmable pin. Configurable to PIN Circuits Pin Circuit Type 1 Port 0 and Port2 PIN Circuits Pin Circuit Type 2 Port 1, Port4, P3.4 and P3.5 Pin Circuit Type 3 P3.0 Pin Circuit Type 4 P3.1 10. Pin Circuit Type 6 nRESET Address Space Overview Program Memory Program Memory Address Space Smart Option Smart Option S3F80JB Address Spaces Summary of S3F80JB Register Type Number of Bytes Register ArchitectureTotal Addressable Bytes 333 Internal Register File Organization Register page Pointer PP Register Page Pointer PP Register SET Prime Register Space Set 1, Set 2, and Prime Area Register Map Working Registers Byte Working Register Areas Slices Using the Register Pointers Programming TIP Setting the Register Pointers #80H RP0 ← 80H R0,R1 ← R0 +R0,R2 R0,R3 Register Addressing Bit Register Pair 10. Register File Addressing Common Working Register Area C0H-CFH RP1 → C8H-CFH Example Programming TIP Addressing the Common Working Register AreaBIT Working Register Addressing 12 -Bit Working Register Addressing 14 -Bit Working Register Addressing 15 -Bit Working Register Addressing Example Stack Operations System and User StacksStack Pointers SPL SPL,#0FFH SPL ← FFH Push RP0Push RP1 POP RP1 Addressing Modes Register Addressing Mode R Register Addressing Indirect Register Addressing Mode IR Indirect Register Addressing to Register File Indirect Register Addressing Mode Indirect Register Addressing to Program Memory Indirect Working Register Addressing to Register File LCD Indexed Addressing Mode Indexed Addressing to Register File Indexed Addressing Mode Next 2 Bits Indexed Addressing to Program or Data Memory Direct Address Mode DA 10. Direct Addressing for Load Instructions Direct Address Mode 11. Direct Addressing for Call and Jump Instructions Indirect Address Mode IA 12. Indirect Addressing Relative Address Mode RA 13. Relative Addressing Immediate Mode IM 14. Immediate Addressing Control Registers T0CNT D0HT0DATA D1H Mapped Registers Register Name Mnemonic Decimal Hex Register Description Format Btcon Basic Timer Control Register D3H Set1 Bank0 Bit Identifier Reset Value Read/Write Addressing ModeWatchdog Timer Function Enable Bits for System Reset Basic Timer Input Clock Selection Bits Cacon Counter a Control Register F3H Set1 Bank0 CPU Clock System Clock Selection Bits Clkcon System Clock Control Register D4H Set1 Bank0Subsystem Clock Selection Bits Cmod Comparator Mode Register E9H Set1 Bank1 Comparator Enable BitConversion Timer Control Bit External Reference Selection Bit Cmpsel Comparator Input Selection Register EBH Set1 Bank1 P2.7 Function Selection BitP2.6 Function Selection Bit P2.5 Function Selection Bit EMT External Memory Timing Register Note FEH Set1 Bank0 Flags System Flags Register D5H Set1 Bank0 Fmcon Flash Memory Control Register EFH Set1 Bank1 Flash Memory Mode Selection BitsOperation stop Operation start auto clear bit Flash Memory Sector Address High Byte Flash Memory User Programming Enable BitsFlash Memory Sector Address Low Byte Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or Overflow Interrupt Level 2 IRQ2 Enable Bit Counter a InterruptInterrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or Overflow IPH Instruction Pointer High Byte DAH Set1 Bank0 IPL Instruction Pointer Low Byte DBH Set1 Bank0Instruction Pointer Address High Byte Instruction Pointer Address Low Byte IPR Interrupt Priority Register FFH Set1 Bank0 IRQ Interrupt Request Register DCH Set1 Bank0 Not pending PendingNot pending Level 2 IRQ2 Request Pending Bit Counter a Interrupt Lvdcon LVD Control Register E0H Set1 Bank1 LVD Flag 2.3V Indicator BitVDD ≥ Lvdflag Level VDD Lvdflag Level P0.7/INT4 Mode Selection Bits P0.6/INT4 Mode Selection BitsP0.5/INT4 Mode Selection Bits P0.4/INT4 Mode Selection Bits P0.3/INT3 Mode Selection Bits P0.2/INT2 Mode Selection BitsP0.1/INT1 Mode Selection Bits P0.0/INT0 Mode Selection Bits P0.7 External Interrupt INT4 Enable Bit P0.6 External Interrupt INT4 Enable BitP0.5 External Interrupt INT4 Enable Bit P0.4 External Interrupt INT4 Enable Bit P0.7 External Interrupt INT4 Pending Flag Bit see Note P0.6 External Interrupt INT4 Pending Flag BitP0.5 External Interrupt INT4 Pending Flag Bit P0.4 External Interrupt INT4 Pending Flag Bit P0.7 Pull-up Resistor Enable Bit P0.6 Pull-up Resistor Enable BitP0.5 Pull-up Resistor Enable Bit P0.4 Pull-up Resistor Enable Bit P1.7 Mode Selection Bits P1.6 Mode Selection BitsP1.5 Mode Selection Bits P1.4 Mode Selection Bits P1.3 Mode Selection Bits P1.2 Mode Selection BitsP1.1 Mode Selection Bits P1.0 Mode Selection Bits P2.7/INT9 Mode Selection Bits P2.6/INT9 Mode Selection BitsP2.5/INT9 Mode Selection Bits P2.4/INT9 Mode Selection Bits P2.3/INT8 Mode Selection Bits P2.2/INT7 Mode Selection BitsP2.1/INT6 Mode Selection Bits P2.0/INT5 Mode Selection Bits P2.7 External Interrupt INT9 Enable Bit P2.6 External Interrupt INT9 Enable BitP2.5 External Interrupt INT9 Enable Bit P2.4 External Interrupt INT9 Enable Bit P2.7 External Interrupt INT9 Pending Flag Bit see Note P2.6 External Interrupt INT9 Pending Flag BitP2.5 External Interrupt INT9 Pending Flag Bit P2.4 External Interrupt INT9 Pending Flag Bit P2.7 Pull-up Resistor Enable Bit P2.6 Pull-up Resistor Enable BitP2.5 Pull-up Resistor Enable Bit P2.4 Pull-up Resistor Enable Bit P3CON Port 3 Control Register EFH Set1 Bank0 P3CON Each Function Description and Assignment to P3.0-P3.3 P3.5 Mode Selection Bits P3.4 Mode Selection BitsP345CON Port345 Control Register E1H Set1 Bank1 Port 4 Control Register Selection Bit P4CON Port 4 Control Register F0H Set1 Bank0 P4.7 Mode Selection Bits P4.6 Mode Selection BitsP4.5 Mode Selection Bits P4.4 Mode Selection Bits P4.3 Mode Selection Bits P4.2 Mode Selection BitsP4.1 Mode Selection Bits P4.0 Mode Selection Bits PP Register Page Pointer DFH Set1 Bank0 Destination page 0 See NoteSource Register Page Selection Bits Source page 0 See Note RP0 Register Pointer D6H Set1 Bank0 RP1 Register Pointer D7H Set1 Bank0Register Pointer 0 Address Value Register Pointer 1 Address Value Stop Control Register Enable Bits SPL Stack Pointer Low Byte D9H Set1 Bank0Stopcon Stop Control Register FBH Set1 Bank0 Stack Pointer Address Low Byte SYM System Mode Register DEH Set1 Bank0 Fast Interrupt Enable BitGlobal Interrupt Enable Bit Tri-State External Interface Control Bit T0CON- Timer 0 Control Register D2H Set 1 Bank0 T1CON Timer 1 Control Register FAH Set1 Bank0 T2CON Timer 2 Control Register E8H Set1 Bank1 Vectors LevelsSources Interrupt Types S3C8/S3F8-Series Interrupt Types S3F80JB Interrupt Structure S3F80JB Interrupt Structure Interrupt Vector Addresses ROM Vector Address Area FCH Interrupt PriorityD8H SYSTEM-LEVEL Interrupt Control Registers ENABLE/DISABLE Interrupt Instructions EI, DIInterrupt Control Register Overview Function Description Interrupt Function Diagram Interrupt Processing Control Points Peripheral Interrupt Control Registers System Mode Register SYM System Mode Register SYM Interrupt Mask Register IMR Interrupt Mask Register IMR Interrupt Priority Register IPR Interrupt Request Priority Groups Interrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQ Pending Bits Cleared by the Service Routine Interrupt Pending Function TypesOverview Pending Bits Cleared Automatically by Hardware Interrupt Service Routines Interrupt Source Polling Sequence Generating Interrupt Vector Addresses Nesting of Vectored InterruptsInstruction Pointer IP Fast Interrupt Processing Procedure for Initiating Fast Interrupt Fast Interrupt Service RoutineFast Interrupt Processing Programming Guidelines Data Types Addressing Modes LDE LDCLded Ldcd Logic Instructions Bit Manipulation Instructions CPU Control Instructions Flags Register Flags System Flags Register Flags Flag Descriptions Instruction SET Notation Instruction Set SymbolsFlag Notation Conventions Immediate addressing mode #data data = Immediate long addressing mode #data data = range@Rn or @reg reg = 0-255, n = Irr Indirect working register pair only @RRp p = 0, 2 Opcode Quick Reference Opcode MAP Lower Nibble HEX Djnz INC Next R1,R2 R2,R1R1,IM Djnz INC NOP Condition Codes Condition Codes Binary Mnemonic Description Flags Set Instruction Descriptions ADC Add with carry FlagsFormat Bytes Cycles Dst Src ADD Add Flags Unaffected Set if the result is 0 cleared otherwise LogicalAlways cleared to Band Bit BCP BCP Bit CompareOperation Bitc Bitc Bit ComplementHex Dst Bitr dst.b Operation dstb ← Bitr Bit ResetFormat Bits Bit Set Bits dst.b Operation dstb ← BOR Bit or BOR Example Given R1 = 07H Btjrf Bit Test, Jump Relative on FalseBtjrf SKIP,R1.3 Btjrt Bit Test, Jump Relative on True Btjrt SKIP,R1.1 Bxor Bit XOR R1,01H.1 R1 = 06H, register 01H = 03H Call Call Call Procedure@SP PCL PCH CCF Complement Carry Flag CCFOperation C ← not C Complemented No other flags are affected CLR dst Operation dst ← CLR Clear00H Register 00H COM Complement COM CP Compare INC Skip LD Cpije Compare, Increment, and Jump on Equal Cpije Cpijne Compare, Increment, and Jump on Non-Equal CpijneIf dst src 0, PC ← PC + RA Instruction DAdst Operation dst ← DA dst DA Decimal AdjustBits R1,R0 R1 ← 3CH +3CH @R1 @R1 ← Leave the value 31 BCD in address 27H @R1 DEC Decrement DECDst Operation ← dst Opc Dst Examples Given R1 = 03H and register 03H = 10H Decw Decrement Word Decw Operation SYM 0 ← DI Disable InterruptsNo flags are affected DIV Divide Unsigned Operation dst ÷ src Djnz Decrement and Jump if Non-Zero Djnz r,dst Operation r ← rJump taken No jump SRP #0C0H Djnz R1,LOOP EI Enable Interrupts Enter Enter EnterOperation SP @SP @IP Exit Exit ExitOperation IP @SP Idle Idle Operation Idle Contents of the destination operand are incremented by one INC IncrementINC dst Operation dst ← dst + = 1CH Incw Increment Word IncwIncw RR0 Loop Incw RR0 Iret Interrupt Return IretFlags ← @SP PC ↔ IP Flags ← Flags JP Jump Labelw Example Given The carry flag = 1 and Labelx = 1FF7H JR Jump RelativeLabelx → PC = 1FF7H LD Load Dst ← src = 0FFH, R1 = 0AH 0AHRegister 31H = 0AH, R0 = 01H, R1 = 0AH LDB Load Bit LDBDst Examples Given R0 = 06H and general register 00H = 05H R0,00H.2 07H, register 00H 05H Addr Mode LDC/LDE Load MemoryLDC/LDE dst,src Operation dst ← src XL L XL H LDC/LDE Examples LDCD/LDED Load Memory and Decrement LDCD/LDED dst,src Operation dst ← src LDCI/LDEI Load Memory and Increment LDCI/LDEI dst,src Operation dst ← srcRr ← rr + Into R8 and RR6 is incremented by one RR6 ← RR6 + Ldcpd LDCPD/LDEPD Load Memory with Pre-DecrementOperation rr ← rr Ldcpi LDCPI/LDEPI Load Memory with Pre-IncrementOperation rr ← rr + RR IML LDW Load WordLDW RR6,RR4 Mult Multiply Unsigned Mult dst,srcOperation dst ← dst ⋅ src Cleared Next Next NextOperation PC ← @ IP NOP No Operation When the instructionNOP Or Logical or POP dst Operation dst ← @SP POP Pop From Stack00H Register 00H 55H, SP = 00FCH Popud Pop User Stack Decrementing Popud dst,src Popui Pop User Stack Incrementing Popui dst,src Push Push To Stack Push src Operation SP ← SPSPH = 0FFH, SPL = 0FFH 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH Pushud Push User Stack Decrementing PushudIR ← IR Decremented stack pointer Pushui Push User Stack Incrementing Pushui dst,src Operation IR ← IR + RCF RCF Reset Carry FlagFlags Cleared to RET Return RETOperation PC ← @SP PC = 101AH, SP = 00FEH RL Rotate Left Dst 0 ← dstDst n + 1 ← dst n, n = Set if the result bit 7 is set cleared otherwise RLC Rotate Left Through Carry RLC RR Rotate Right RR dstOperation C ← dst Rotation cleared otherwise RRC Rotate Right Through Carry RRCDst 7 ← C 00H Register 00H 2AH, C = SB0 Select Bank SB0Operation Bank ← Statement SB1 Select Bank SB1 Always set to SBC Subtract With CarrySet otherwise, indicating a borrow Format Bytes Cycles SCF Set Carry Flag SCFSet to No other flags are affected Sets the carry flag to logic one SRA dst SRA Shift Right Arithmetic00H Register 00H 0CD, C = SRP/SRP0/SRP1 Set Register Pointer SRPSRP0 SRP1 Stop Stop Operation Stop SUB SUB SubtractSet otherwise indicating a borrow Format Bytes Cycles Swap Swap Nibbles Swap dstFlags Undefined Set if the result is 0 cleared otherwise 00H Register 00H 0E3H TCM Test Complement Under Mask R0,R1 = 0C7H, R1 = 02H, Z =R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z = 00H,01H Register 00H = 2BH, register 01H = 02H, Z = Always reset to TM Test Under MaskTMdst,src Operation dst and src WFI WFI Wait For InterruptOpc 4n 3F XOR XOR Logical Exclusive or7FH Clock Circuits System Clock Circuit Clock Status During POWER-DOWN Modes System Clock Circuit Diagram System Clock Control Register Clkcon System Clock Control Register Clkcon Reset Reset Sources EIexternal interrupt enable Reset Sources of The S3F80JB Reset Block Diagram of The S3F80JB Reset Mechanism External Reset PINWatch DOG Timer Reset LVD Reset Internal POWER-ON Reset Internal Power-On Reset Circuit Timing Diagram for Internal Power-On Reset Circuit Reset Timing Diagram for The S3F80JB in Stop mode by Ipor External Interrupt Reset Stop Error Detection & Recovery VresetReset Source Slope of V DD Idle Mode POWER-DOWN ModesIdle Mode Release BACK-UP Mode Block Diagram for Back-up Mode Stop Mode Programming TIP To Enter Stop Mode Sources to Release Stop Mode Using nRESET Pin to Release Stop ModeUsing Ipor to Release Stop Mode Using LVD to Release Stop Mode SED&R Stop Error Detect and Recovery System Reset Operation Hardware Reset Values Dec Timer 1 Data Register High Byte Timer 1 Data Register Low ByteTimer 1 Control Register Dec Hex Timer 2 Counter Register Low Byte Timer 2 Data Register High ByteTimer 2 Data Register Low Byte Timer 2 Control Register Ipor LVDStop Ipor SED&R Recommendation for Unusued Pins ← # 0FFHP2PUR Connect to VSS Summary Table of BACK-UP MODE, Stop MODE, and Reset Status Summary of Each Mode Item/Mode Back-up Reset Status StopStopcon ← # A5H LD STOPCON,#0A5H O Ports S3F80JB Port Configuration Overview 44-QFP Port Configuration OptionsAssigned individually as analog input pin for comparator P3.0-P3.1 S3F80JB Port Configuration Overview 32-SOP Port Data Registers S3F80JB I/O Port Data Register Format PULL-UP Resistor Enable Registers Pull-up Resistor Enable Registers Port 0 and Port 2 only Basic Timer BT Timer Basic Timer Control Register Btcon Basic Timer Control Register Btcon Watch-dog Timer Function Basic Timer Function DescriptionOscillation Stabilization Interval Timer Function Timer 0 Control Register T0CON Timer 0 Control Register T0CON Timer 0 Interrupts IRQ0, Vectors FAH and FCH Timer 0 Function DescriptionInterval Timer Mode Pulse Width Modulation Mode Simplified Timer 0 Function Diagram PWM Mode Capture Mode Simplified Timer 0 Function Diagram Capture Mode Basic Timer and Timer 0 Block Diagram Programming TIP Configuring the Basic Timer CLR SYMCLR SPL Main BTCON,#52H Programming TIP Programming Timer NO200MSSET ULT,NO200MSSET BitsT0OVER Iret Timer Timer 1 Overflow Interrupt Timer 1 Capture Interrupt Timer 1 Match Interrupt Simplified Timer 1 Function Diagram Interval Timer Mode Timer 1 Block Diagram Timer 1 Control Register T1CON Timer 1 Control Register T1CON Timer 1 Registers T1CNTH, T1CNTL, T1DATAH, T1DATAL Counter a Counter a Block Diagram Counter a Control Register Cacon Counter a Control Register Cacon Method 2 When Caof = Counter a Pulse Width Calculations Counter a Output Flip-Flop Waveforms in Repeat Mode Through P3.1 Programming TIP To generate a one-pulse signal through P3.1 CADATAH,# Set 40 msCADATAL,# Set any value except 00H 13-1 Timer 2 Overflow Interrupt Timer 2 Capture Interrupt Timer 2 Match Interrupt Simplified Timer 2 Function Diagram Interval Timer Mode Timer 2 Block Diagram Timer 2 Control Register T2CON Timer 2 Control Register T2CON Timer 2 Registers T2CNTH, T2CNTL, T2DATAH, T2DATAL Comparator Comparator Block Diagram for The S3F80JB Conversion Characteristics Comparator Operation Comparator Mode Register Cmod Comparator Result Register Cmpreg Flash ROM Configuration Embedded Flash Memory Interface Tool Program Mode User Program ModePin No Function Isptm ON-BOARD Programming Sector 15-4 ISP Reset Vector and ISP Sector Size ISP Sector SizeArea of ISP Sector ISP Sector Size Bit Flash Memory User Programming Enable Register Fmusr Flash Memory Control Registers User Program ModeFlash Memory Control Register Fmcon Flash Memory Sector Address Registers Flash Memory Sector Address Register Fmsech Sector Configurations in User Program Mode Sector Erase Sector Erase Procedure in User Program Mode Sector Erase Flowchart in User Program Mode Programming TIP Sector Erase Case1. Erase one sector Sectorerase Btjrf FLAGS.7,NOCARRYNocarry Erasestart SB1 FMUSR,#0A5H Program procedure in user program mode Programming Byte Program Flowchart in a User Program Mode 10. Program Flowchart in a User Program Mode Programming TIP Programming Case1 -Byte Programming Case2. Programming in the same sector WRINSECTOR2 LD FMSECH,#01HCall Wrbyte WRINSECTOR50 FMSECH,#19H Reading Programming TIP ReadingLoop LDC NZ,LOOP Programming TIP Hard Lock Protection Hard Lock ProtectionFMCON,#01100001B LVD LVD Flag Resistor String LOW Voltage Detector Control Register Lvdcon Low Voltage Detect Control Register Lvdcon Electrical Data 4MHz Parameter Symbol Conditions Rating Unit D.C. Electrical CharacteristicsParameter Symbol Conditions Min Typ Max Unit Absolute Maximum Ratings Leakage Current All input pins except ILIH2 and Xout Leakage Current All output pins Output LowVout = 0 Leakage Current All output pins Pull-Up Output Low Characteristics of Low Voltage Detect Circuit Parameter Symbol ConditionsData Retention Supply Voltage in Stop Mode Min Typ Max Unit Typical Low-Side Driver Sink Characteristics P3.1 only Typical High-Side Driver Source Characteristics P3.1 only Typical VDD-VOHVDD=3.3V Stop Mode Release Timing When Initiated by a Reset A.C. Electrical Characteristics 10. Input Timing for External Interrupts Port 0 and Port Oscillation Characteristics Oscillator Clock Circuit Conditions Min Typ Max Unit When released by a reset 216/f Stabilization Wait time TWAIT when released by an interruptOscillation Stabilization Time TA = 25 C to + 85 C, VDD = 3.6 100 Data Access Time Sector Erasing TimeChip Erasing Time VDD = 2.0 250 Number of Writing/Erasing FNwe 10,000 Electrical Data 8MHZ TA = 25 C to + 85 C, VDD = 1.95 V to 3.6 Fosc = 8 MHz Input High VoltageVDD = 2.35 V, IOH = 6mA VDD = 2.35 V, IOH = 2.2mA P3.0 and P2.0-2.3 Leakage Current All input pins except ILIH2 Leakage Current All input pins except ILIL2Leakage Current All output pins Pull-Up Resistors VDD = 2.35 V, IOL = 12mA Operating Mode DD = 3.6 MHz crystal Idle Mode DD =3.6 MHz crystalStop Mode LVD OFF, V DD = 3.6 LVD ON, V DD = 3.6 For Back-Up Mode Low Level Detect Voltage Vddv Typical VDD-VOHVDD=3.3V VDD-VOHV Typical VDD-VOHVDD=3.3VIOHmA 18-8 18-9 18-10 Comparator Electrical Characteristics Parameter Symbol Condition Min Typ Max Units TA = -25 C to + 85 C, VDD = 3.6 Flash Erase/Write/Read Voltage Fewrv 18-14 Pin SOP Package Dimension SOP-450A QFP-1010B Target Boards Programming Socket Adapter TB80JB Target Board Configuration TB80JB Target Board Components Consisting of S3F80JB Target Board Block Symbols J1AVCC, GND, S IDLE, Stop LED Idle LED JP#Stop LED Pin Connector Pin Assignment for TB80JB Series In-Circuit Emulator OTP/MTP ProgrammerGW-PRO2 Development Tools Suppliers Seminix OTP/MTP Programmer Writer SPW2+GW-PRO2 For what kind of product will you be using this order? Product descriptionPackage Marking Check One Customer sample Risk order Risk Order Information Customer Risk Order AgreementOrder Quantity and Delivery Schedule Delivery Date s Quantity Comments Signatures Flash Application Notes VDD S3F80JB Important Note For Serial Programming Mode S3F80JB/9 is needed to nRESET pin = 0GND & Test pin = 1VDD For Normal Operating Mode S3F80JB/9 is needed to nRESET pin = 1VDD & Test pin = 0GNDWhen nRESET pin = 1VDD & Test pin = 0GND Timing Diagram When Test PIN = 1VDD ¾ When S3F80JB ¾ When S3F80J9