S3F80JB
Important Notice
Part Programming Model
Reset
Table of Contents
Interrupt Structure
Summary Table of Back-Up Mode, Stop Mode, and Reset Status
Reset
10-1
Timer
10-2
10-3
15-1
Flash Memory User Programming Enable Register Fmusr 15-6
15-3
15-5
Title Number
List of Figures
10-7
10-5
10-8
10-9
17-6 Typical High-Side Driver Source Characteristics
17-3 Typical Low-Side Driver Sink Characteristics
12-2
12-5
18-6 Typical High-Side Driver Source Characteristics
18-3 Typical Low-Side Driver Sink Characteristics
18-2
18-4
List of Tables
Reset Condition in Stop Mode When Ipor / LVD Control Bit is
17-6
17-3
17-13
18-3
Chapter Basic Timer and Timer
Chapter Reset
Description
Chapter Address Spaces
Register Full Register Name Identifier
Instruction Full Register Name Mnemonic
NOP
Next
POP
Popud
S3F80JB Microcontroller
S3C8/S3F8-SERIES Microcontrollers
CPU
Features
Block Diagram 32-pin
Block Diagram 32-PIN Package
Block Diagram 44-pin
Block Diagram 44-PIN Package
PIN Assignments
Pin Assignment Diagram 32-Pin SOP Package
S3F80JB
PIN Assignments
44-QFP
Pin Descriptions of 32-SOP Circuit 32 Pin Shared Names
Pin Descriptions of 44-QFP Circuit 44 Pin Shared Names
P3.1 Port with bit-programmable pin. Configurable to
Pin Circuit Type 1 Port 0 and Port2
PIN Circuits
Pin Circuit Type 2 Port 1, Port4, P3.4 and P3.5
PIN Circuits
Pin Circuit Type 3 P3.0
Pin Circuit Type 4 P3.1
10. Pin Circuit Type 6 nRESET
Overview
Address Space
Program Memory Address Space
Program Memory
Smart Option
Smart Option
S3F80JB Address Spaces
Summary of S3F80JB Register Type Number of Bytes
Register Architecture
Total Addressable Bytes 333
Internal Register File Organization
Register Page Pointer PP
Register page Pointer PP
Register SET
Set 1, Set 2, and Prime Area Register Map
Prime Register Space
Byte Working Register Areas Slices
Working Registers
Programming TIP Setting the Register Pointers
Using the Register Pointers
R0,R1 ← R0 +
#80H RP0 ← 80H
R0,R2
R0,R3
Bit Register Pair
Register Addressing
10. Register File Addressing
RP1 → C8H-CFH
Common Working Register Area C0H-CFH
Example
Programming TIP Addressing the Common Working Register Area
BIT Working Register Addressing
12 -Bit Working Register Addressing
14 -Bit Working Register Addressing
15 -Bit Working Register Addressing Example
Stack Operations
System and User Stacks
Stack Pointers SPL
Push RP0
SPL,#0FFH SPL ← FFH
Push RP1
POP RP1
Addressing Modes
Register Addressing
Register Addressing Mode R
Indirect Register Addressing to Register File
Indirect Register Addressing Mode IR
Indirect Register Addressing to Program Memory
Indirect Register Addressing Mode
Indirect Working Register Addressing to Register File
LCD
Indexed Addressing to Register File
Indexed Addressing Mode
Next 2 Bits
Indexed Addressing Mode
Indexed Addressing to Program or Data Memory
10. Direct Addressing for Load Instructions
Direct Address Mode DA
11. Direct Addressing for Call and Jump Instructions
Direct Address Mode
12. Indirect Addressing
Indirect Address Mode IA
13. Relative Addressing
Relative Address Mode RA
14. Immediate Addressing
Immediate Mode IM
Control Registers
D0H
T0CNT
T0DATA
D1H
Mapped Registers Register Name Mnemonic Decimal Hex
Register Description Format
Bit Identifier Reset Value Read/Write Addressing Mode
Btcon Basic Timer Control Register D3H Set1 Bank0
Watchdog Timer Function Enable Bits for System Reset
Basic Timer Input Clock Selection Bits
Cacon Counter a Control Register F3H Set1 Bank0
CPU Clock System Clock Selection Bits
Clkcon System Clock Control Register D4H Set1 Bank0
Subsystem Clock Selection Bits
Comparator Enable Bit
Cmod Comparator Mode Register E9H Set1 Bank1
Conversion Timer Control Bit
External Reference Selection Bit
P2.7 Function Selection Bit
Cmpsel Comparator Input Selection Register EBH Set1 Bank1
P2.6 Function Selection Bit
P2.5 Function Selection Bit
EMT External Memory Timing Register Note FEH Set1 Bank0
Flags System Flags Register D5H Set1 Bank0
Fmcon Flash Memory Control Register EFH Set1 Bank1
Flash Memory Mode Selection Bits
Operation stop Operation start auto clear bit
Flash Memory Sector Address High Byte
Flash Memory User Programming Enable Bits
Flash Memory Sector Address Low Byte
Interrupt Level 2 IRQ2 Enable Bit Counter a Interrupt
Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or Overflow
Interrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow
Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or Overflow
IPL Instruction Pointer Low Byte DBH Set1 Bank0
IPH Instruction Pointer High Byte DAH Set1 Bank0
Instruction Pointer Address High Byte
Instruction Pointer Address Low Byte
IPR Interrupt Priority Register FFH Set1 Bank0
Not pending Pending
IRQ Interrupt Request Register DCH Set1 Bank0
Not pending
Level 2 IRQ2 Request Pending Bit Counter a Interrupt
Lvdcon LVD Control Register E0H Set1 Bank1
LVD Flag 2.3V Indicator Bit
VDD ≥ Lvdflag Level VDD Lvdflag Level
P0.6/INT4 Mode Selection Bits
P0.7/INT4 Mode Selection Bits
P0.5/INT4 Mode Selection Bits
P0.4/INT4 Mode Selection Bits
P0.2/INT2 Mode Selection Bits
P0.3/INT3 Mode Selection Bits
P0.1/INT1 Mode Selection Bits
P0.0/INT0 Mode Selection Bits
P0.6 External Interrupt INT4 Enable Bit
P0.7 External Interrupt INT4 Enable Bit
P0.5 External Interrupt INT4 Enable Bit
P0.4 External Interrupt INT4 Enable Bit
P0.6 External Interrupt INT4 Pending Flag Bit
P0.7 External Interrupt INT4 Pending Flag Bit see Note
P0.5 External Interrupt INT4 Pending Flag Bit
P0.4 External Interrupt INT4 Pending Flag Bit
P0.6 Pull-up Resistor Enable Bit
P0.7 Pull-up Resistor Enable Bit
P0.5 Pull-up Resistor Enable Bit
P0.4 Pull-up Resistor Enable Bit
P1.6 Mode Selection Bits
P1.7 Mode Selection Bits
P1.5 Mode Selection Bits
P1.4 Mode Selection Bits
P1.2 Mode Selection Bits
P1.3 Mode Selection Bits
P1.1 Mode Selection Bits
P1.0 Mode Selection Bits
P2.6/INT9 Mode Selection Bits
P2.7/INT9 Mode Selection Bits
P2.5/INT9 Mode Selection Bits
P2.4/INT9 Mode Selection Bits
P2.2/INT7 Mode Selection Bits
P2.3/INT8 Mode Selection Bits
P2.1/INT6 Mode Selection Bits
P2.0/INT5 Mode Selection Bits
P2.6 External Interrupt INT9 Enable Bit
P2.7 External Interrupt INT9 Enable Bit
P2.5 External Interrupt INT9 Enable Bit
P2.4 External Interrupt INT9 Enable Bit
P2.6 External Interrupt INT9 Pending Flag Bit
P2.7 External Interrupt INT9 Pending Flag Bit see Note
P2.5 External Interrupt INT9 Pending Flag Bit
P2.4 External Interrupt INT9 Pending Flag Bit
P2.6 Pull-up Resistor Enable Bit
P2.7 Pull-up Resistor Enable Bit
P2.5 Pull-up Resistor Enable Bit
P2.4 Pull-up Resistor Enable Bit
P3CON Port 3 Control Register EFH Set1 Bank0
Each Function Description and Assignment to P3.0-P3.3
P3CON
P3.4 Mode Selection Bits
P3.5 Mode Selection Bits
P345CON Port345 Control Register E1H Set1 Bank1
Port 4 Control Register Selection Bit
P4CON Port 4 Control Register F0H Set1 Bank0
P4.6 Mode Selection Bits
P4.7 Mode Selection Bits
P4.5 Mode Selection Bits
P4.4 Mode Selection Bits
P4.2 Mode Selection Bits
P4.3 Mode Selection Bits
P4.1 Mode Selection Bits
P4.0 Mode Selection Bits
Destination page 0 See Note
PP Register Page Pointer DFH Set1 Bank0
Source Register Page Selection Bits
Source page 0 See Note
RP1 Register Pointer D7H Set1 Bank0
RP0 Register Pointer D6H Set1 Bank0
Register Pointer 0 Address Value
Register Pointer 1 Address Value
SPL Stack Pointer Low Byte D9H Set1 Bank0
Stop Control Register Enable Bits
Stopcon Stop Control Register FBH Set1 Bank0
Stack Pointer Address Low Byte
Fast Interrupt Enable Bit
SYM System Mode Register DEH Set1 Bank0
Global Interrupt Enable Bit
Tri-State External Interface Control Bit
T0CON- Timer 0 Control Register D2H Set 1 Bank0
T1CON Timer 1 Control Register FAH Set1 Bank0
T2CON Timer 2 Control Register E8H Set1 Bank1
Vectors
Levels
Sources
S3C8/S3F8-Series Interrupt Types
Interrupt Types
S3F80JB Interrupt Structure
S3F80JB Interrupt Structure
ROM Vector Address Area
Interrupt Vector Addresses
FCH
Interrupt Priority
D8H
SYSTEM-LEVEL Interrupt Control Registers
ENABLE/DISABLE Interrupt Instructions EI, DI
Interrupt Control Register Overview Function Description
Interrupt Processing Control Points
Interrupt Function Diagram
Peripheral Interrupt Control Registers
System Mode Register SYM
System Mode Register SYM
Interrupt Mask Register IMR
Interrupt Mask Register IMR
Interrupt Request Priority Groups
Interrupt Priority Register IPR
Interrupt Priority Register IPR
Interrupt Request Register IRQ
Interrupt Request Register IRQ
Interrupt Pending Function Types
Pending Bits Cleared by the Service Routine
Overview
Pending Bits Cleared Automatically by Hardware
Interrupt Source Polling Sequence
Interrupt Service Routines
Nesting of Vectored Interrupts
Generating Interrupt Vector Addresses
Instruction Pointer IP
Fast Interrupt Processing
Fast Interrupt Service Routine
Procedure for Initiating Fast Interrupt
Fast Interrupt Processing
Programming Guidelines
Addressing Modes
Data Types
LDC
LDE
Lded
Ldcd
Logic Instructions
Bit Manipulation Instructions
CPU Control Instructions
System Flags Register Flags
Flags Register Flags
Flag Descriptions
Instruction SET Notation
Instruction Set Symbols
Flag Notation Conventions
Immediate long addressing mode #data data = range
Immediate addressing mode #data data =
@Rn or @reg reg = 0-255, n =
Irr Indirect working register pair only @RRp p = 0, 2
Opcode MAP Lower Nibble HEX
Opcode Quick Reference
R1,R2 R2,R1
Djnz INC Next
R1,IM
Djnz INC NOP
Condition Codes Binary Mnemonic Description Flags Set
Condition Codes
Instruction Descriptions
Flags
ADC Add with carry
Format Bytes Cycles
Dst Src
ADD Add
Flags Unaffected Set if the result is 0 cleared otherwise
Logical
Always cleared to
Band Bit
BCP
BCP Bit Compare
Operation
Bitc
Bitc Bit Complement
Hex Dst
Bitr dst.b Operation dstb ←
Bitr Bit Reset
Format
Bits dst.b Operation dstb ←
Bits Bit Set
BOR
BOR Bit or
Example Given R1 = 07H
Btjrf Bit Test, Jump Relative on False
Btjrf SKIP,R1.3
Btjrt SKIP,R1.1
Btjrt Bit Test, Jump Relative on True
R1,01H.1 R1 = 06H, register 01H = 03H
Bxor Bit XOR
Call
Call Call Procedure
@SP PCL PCH
CCF
CCF Complement Carry Flag
Operation C ← not C
Complemented No other flags are affected
CLR dst Operation dst ←
CLR Clear
00H Register 00H
COM
COM Complement
INC Skip LD
CP Compare
Cpije
Cpije Compare, Increment, and Jump on Equal
Cpijne
Cpijne Compare, Increment, and Jump on Non-Equal
If dst src 0, PC ← PC + RA
Instruction
DAdst Operation dst ← DA dst
DA Decimal Adjust
Bits
R1 ← 3CH +
R1,R0
3CH
@R1 @R1 ← Leave the value 31 BCD in address 27H @R1
DEC
DEC Decrement
Dst Operation ← dst
Opc Dst Examples Given R1 = 03H and register 03H = 10H
Decw
Decw Decrement Word
Operation SYM 0 ←
DI Disable Interrupts
No flags are affected
Operation dst ÷ src
DIV Divide Unsigned
Djnz r,dst Operation r ← r
Djnz Decrement and Jump if Non-Zero
Jump taken No jump
SRP #0C0H Djnz R1,LOOP
EI Enable Interrupts
Enter
Enter Enter
Operation SP
@SP @IP
Exit
Exit Exit
Operation IP
@SP
Idle
Idle Idle Operation
INC Increment
Contents of the destination operand are incremented by one
INC dst Operation dst ← dst +
= 1CH
Incw
Incw Increment Word
Incw RR0
Loop Incw RR0
Iret
Iret Interrupt Return
Flags ← @SP PC ↔ IP
Flags ← Flags
Labelw
JP Jump
Example Given The carry flag = 1 and Labelx = 1FF7H
JR Jump Relative
Labelx → PC = 1FF7H
Dst ← src
LD Load
= 0FFH, R1 = 0AH
0AH
Register 31H = 0AH, R0 = 01H, R1 = 0AH
LDB
LDB Load Bit
Dst Examples Given R0 = 06H and general register 00H = 05H
R0,00H.2 07H, register 00H 05H
LDC/LDE Load Memory
Addr Mode
LDC/LDE dst,src Operation dst ← src
XL L XL H
Examples
LDC/LDE
LDCD/LDED dst,src Operation dst ← src
LDCD/LDED Load Memory and Decrement
LDCI/LDEI dst,src Operation dst ← src
LDCI/LDEI Load Memory and Increment
Rr ← rr +
Into R8 and RR6 is incremented by one RR6 ← RR6 +
Ldcpd
LDCPD/LDEPD Load Memory with Pre-Decrement
Operation rr ← rr
Ldcpi
LDCPI/LDEPI Load Memory with Pre-Increment
Operation rr ← rr +
RR IML
LDW Load Word
LDW RR6,RR4
Mult dst,src
Mult Multiply Unsigned
Operation dst ← dst ⋅ src
Cleared
Next
Next Next
Operation PC ← @ IP
NOP No Operation
When the instruction
NOP
Or Logical or
POP dst Operation dst ← @SP
POP Pop From Stack
00H Register 00H 55H, SP = 00FCH
Popud dst,src
Popud Pop User Stack Decrementing
Popui dst,src
Popui Pop User Stack Incrementing
Push src Operation SP ← SP
Push Push To Stack
SPH = 0FFH, SPL = 0FFH
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
Pushud
Pushud Push User Stack Decrementing
IR ← IR
Decremented stack pointer
Pushui dst,src Operation IR ← IR +
Pushui Push User Stack Incrementing
RCF
RCF Reset Carry Flag
Flags Cleared to
RET
RET Return
Operation PC ← @SP
PC = 101AH, SP = 00FEH
Dst 0 ← dst
RL Rotate Left
Dst n + 1 ← dst n, n =
Set if the result bit 7 is set cleared otherwise
RLC
RLC Rotate Left Through Carry
RR dst
RR Rotate Right
Operation C ← dst
Rotation cleared otherwise
RRC
RRC Rotate Right Through Carry
Dst 7 ← C
00H Register 00H 2AH, C =
SB0
SB0 Select Bank
Operation Bank ←
Statement
SB1
SB1 Select Bank
Always set to
SBC Subtract With Carry
Set otherwise, indicating a borrow Format Bytes Cycles
SCF
SCF Set Carry Flag
Set to No other flags are affected
Sets the carry flag to logic one
SRA dst
SRA Shift Right Arithmetic
00H Register 00H 0CD, C =
SRP
SRP/SRP0/SRP1 Set Register Pointer
SRP0
SRP1
Stop
Stop Stop Operation
SUB
SUB Subtract
Set otherwise indicating a borrow Format Bytes Cycles
Swap dst
Swap Swap Nibbles
Flags Undefined Set if the result is 0 cleared otherwise
00H Register 00H 0E3H
R0,R1 = 0C7H, R1 = 02H, Z =
TCM Test Complement Under Mask
R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z =
00H,01H Register 00H = 2BH, register 01H = 02H, Z =
TM Test Under Mask
Always reset to
TMdst,src
Operation dst and src
WFI
WFI Wait For Interrupt
Opc 4n 3F
XOR
XOR Logical Exclusive or
7FH
System Clock Circuit
Clock Circuits
System Clock Circuit Diagram
Clock Status During POWER-DOWN Modes
System Clock Control Register Clkcon
System Clock Control Register Clkcon
Reset Sources
Reset
Reset Sources of The S3F80JB
EIexternal interrupt enable
Reset Block Diagram of The S3F80JB
External Reset PIN
Reset Mechanism
Watch DOG Timer Reset
LVD Reset
Internal Power-On Reset Circuit
Internal POWER-ON Reset
Timing Diagram for Internal Power-On Reset Circuit
External Interrupt Reset
Reset Timing Diagram for The S3F80JB in Stop mode by Ipor
Vreset
Stop Error Detection & Recovery
Reset Source
Slope of V DD
Idle Mode
POWER-DOWN Modes
Idle Mode Release
Block Diagram for Back-up Mode
BACK-UP Mode
Programming TIP To Enter Stop Mode
Stop Mode
Using nRESET Pin to Release Stop Mode
Sources to Release Stop Mode
Using Ipor to Release Stop Mode
Using LVD to Release Stop Mode
SED&R Stop Error Detect and Recovery
System Reset Operation
Dec
Hardware Reset Values
Timer 1 Data Register Low Byte
Timer 1 Data Register High Byte
Timer 1 Control Register
Dec Hex
Timer 2 Data Register High Byte
Timer 2 Counter Register Low Byte
Timer 2 Data Register Low Byte
Timer 2 Control Register
LVD
Ipor
Stop Ipor
SED&R
← # 0FFH
Recommendation for Unusued Pins
P2PUR
Connect to VSS
Summary of Each Mode Item/Mode Back-up Reset Status Stop
Summary Table of BACK-UP MODE, Stop MODE, and Reset Status
Stopcon ← # A5H
LD STOPCON,#0A5H
O Ports
Port Configuration Options
S3F80JB Port Configuration Overview 44-QFP
Assigned individually as analog input pin for comparator
P3.0-P3.1
S3F80JB Port Configuration Overview 32-SOP
S3F80JB I/O Port Data Register Format
Port Data Registers
Pull-up Resistor Enable Registers Port 0 and Port 2 only
PULL-UP Resistor Enable Registers
Timer
Basic Timer BT
Basic Timer Control Register Btcon
Basic Timer Control Register Btcon
Watch-dog Timer Function
Basic Timer Function Description
Oscillation Stabilization Interval Timer Function
Timer 0 Control Register T0CON
Timer 0 Control Register T0CON
Timer 0 Interrupts IRQ0, Vectors FAH and FCH
Timer 0 Function Description
Interval Timer Mode
Simplified Timer 0 Function Diagram PWM Mode
Pulse Width Modulation Mode
Simplified Timer 0 Function Diagram Capture Mode
Capture Mode
Basic Timer and Timer 0 Block Diagram
CLR SYM
Programming TIP Configuring the Basic Timer
CLR SPL
Main BTCON,#52H
Programming TIP Programming Timer
NO200MSSET
ULT,NO200MSSET Bits
T0OVER Iret
Timer
Timer 1 Capture Interrupt
Timer 1 Overflow Interrupt
Simplified Timer 1 Function Diagram Interval Timer Mode
Timer 1 Match Interrupt
Timer 1 Block Diagram
Timer 1 Control Register T1CON
Timer 1 Control Register T1CON
Timer 1 Registers T1CNTH, T1CNTL, T1DATAH, T1DATAL
Counter a
Counter a Block Diagram
Counter a Control Register Cacon
Counter a Control Register Cacon
Counter a Pulse Width Calculations
Method 2 When Caof =
Counter a Output Flip-Flop Waveforms in Repeat Mode
Through P3.1
CADATAH,# Set 40 ms
Programming TIP To generate a one-pulse signal through P3.1
CADATAL,#
Set any value except 00H
13-1
Timer 2 Capture Interrupt
Timer 2 Overflow Interrupt
Simplified Timer 2 Function Diagram Interval Timer Mode
Timer 2 Match Interrupt
Timer 2 Block Diagram
Timer 2 Control Register T2CON
Timer 2 Control Register T2CON
Timer 2 Registers T2CNTH, T2CNTL, T2DATAH, T2DATAL
Comparator
Comparator Block Diagram for The S3F80JB
Comparator Operation
Conversion Characteristics
Comparator Mode Register Cmod
Comparator Result Register Cmpreg
Embedded Flash Memory Interface
Flash ROM Configuration
Tool Program Mode
User Program Mode
Pin No Function
Isptm ON-BOARD Programming Sector
15-4
ISP Sector Size
ISP Reset Vector and ISP Sector Size
Area of ISP Sector ISP Sector Size
Bit
Flash Memory User Programming Enable Register Fmusr
Flash Memory Control Registers User Program Mode
Flash Memory Control Register Fmcon
Flash Memory Sector Address Register Fmsech
Flash Memory Sector Address Registers
Sector Erase
Sector Configurations in User Program Mode
Sector Erase Flowchart in User Program Mode
Sector Erase Procedure in User Program Mode
Programming TIP Sector Erase Case1. Erase one sector
Btjrf FLAGS.7,NOCARRY
Sectorerase
Nocarry
Erasestart SB1 FMUSR,#0A5H
Programming
Program procedure in user program mode
Byte Program Flowchart in a User Program Mode
10. Program Flowchart in a User Program Mode
Case2. Programming in the same sector
Programming TIP Programming Case1 -Byte Programming
LD FMSECH,#01H
WRINSECTOR2
Call Wrbyte
WRINSECTOR50 FMSECH,#19H
Programming TIP Reading
Reading
Loop LDC
NZ,LOOP
Programming TIP Hard Lock Protection
Hard Lock Protection
FMCON,#01100001B
LVD Flag
LVD
Resistor String
Low Voltage Detect Control Register Lvdcon
LOW Voltage Detector Control Register Lvdcon
Electrical Data 4MHz
D.C. Electrical Characteristics
Parameter Symbol Conditions Rating Unit
Parameter Symbol Conditions Min Typ Max Unit
Absolute Maximum Ratings
Leakage Current All output pins Output Low
Leakage Current All input pins except ILIH2 and Xout
Vout = 0 Leakage Current All output pins Pull-Up
Output Low
Parameter Symbol Conditions
Characteristics of Low Voltage Detect Circuit
Data Retention Supply Voltage in Stop Mode
Min Typ Max Unit
Typical Low-Side Driver Sink Characteristics P3.1 only
Typical High-Side Driver Source Characteristics P3.1 only
Typical VDD-VOHVDD=3.3V
Stop Mode Release Timing When Initiated by a Reset
A.C. Electrical Characteristics
10. Input Timing for External Interrupts Port 0 and Port
Oscillator Clock Circuit Conditions Min Typ Max Unit
Oscillation Characteristics
Wait time TWAIT when released by an interrupt
When released by a reset 216/f Stabilization
Oscillation Stabilization Time
TA = 25 C to + 85 C, VDD = 3.6
Sector Erasing Time
100 Data Access Time
Chip Erasing Time
VDD = 2.0 250 Number of Writing/Erasing FNwe 10,000
Electrical Data 8MHZ
Fosc = 8 MHz Input High Voltage
TA = 25 C to + 85 C, VDD = 1.95 V to 3.6
VDD = 2.35 V, IOH = 6mA
VDD = 2.35 V, IOH = 2.2mA P3.0 and P2.0-2.3
Leakage Current All input pins except ILIL2
Leakage Current All input pins except ILIH2
Leakage Current All output pins Pull-Up Resistors
VDD = 2.35 V, IOL = 12mA
Idle Mode DD =3.6 MHz crystal
Operating Mode DD = 3.6 MHz crystal
Stop Mode LVD OFF, V DD = 3.6 LVD ON, V DD = 3.6
For Back-Up Mode Low Level Detect Voltage
Vddv
Typical VDD-VOHVDD=3.3V
VDD-VOHV
Typical VDD-VOHVDD=3.3V
IOHmA
18-8
18-9
18-10
Parameter Symbol Condition Min Typ Max Units
Comparator Electrical Characteristics
TA = -25 C to + 85 C, VDD = 3.6
Flash Erase/Write/Read Voltage Fewrv
18-14
SOP-450A
Pin SOP Package Dimension
QFP-1010B
Programming Socket Adapter
Target Boards
TB80JB Target Board
TB80JB Target Board Configuration
J1A
Components Consisting of S3F80JB Target Board Block Symbols
VCC, GND, S
IDLE, Stop LED
Idle LED
JP#
Stop LED
Pin Connector Pin Assignment for TB80JB
OTP/MTP Programmer
Series In-Circuit Emulator
GW-PRO2
Development Tools Suppliers
Seminix
OTP/MTP Programmer Writer SPW2+
GW-PRO2
Product description
For what kind of product will you be using this order?
Package Marking Check One
Customer sample Risk order
Customer Risk Order Agreement
Risk Order Information
Order Quantity and Delivery Schedule
Delivery Date s Quantity Comments Signatures
Flash Application Notes
VDD
S3F80JB
Important Note
S3F80JB/9 is needed to nRESET pin = 0GND & Test pin = 1VDD
For Serial Programming Mode
S3F80JB/9 is needed to nRESET pin = 1VDD & Test pin = 0GND
For Normal Operating Mode
When nRESET pin = 1VDD & Test pin = 0GND
Timing Diagram
¾ When S3F80JB
When Test PIN = 1VDD
¾ When S3F80J9