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Samsung S3F80JB manual SED&R Stop Error Detect and Recovery

Models: S3F80JB

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S3F80JB	RESET

SED&R (Stop Error Detect and Recovery)

The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0 and P2.4-P2.7. One is releasing from stop status by switching the level of input port (P0 or P2.4-P2.7) and the other is keeping the chip from the stop mode when the chip is in abnormal status.

—Releasing from stop mode

When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’, if falling edge input signal enters in through Port0 or P2.4-P2.7, S3F80JB is released stop mode and generate reset signal. On the other hand, when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop mode. Reset doesn’t occur. When the falling edge of a pin on Port0 and P2.4-P2.7 is entered, the chip is released from stop mode even though external interrupt is disabled.

—Keeping the chip from entering abnormal - stop mode

This circuit detects the abnormal status by checking the port (P0 and P2.4-P2.7) status. If the chip is in abnormal status it keeps from entering stop mode.

NOTE

In case of P2.0-2.3, SED&R circuit isn’t implemented. So although 4pins, P2.0-2.3, have the falling edge input signal in stop mode, if external interrupt is disabled, the stop state of S3F80JB is unchanged. Do not use stop mode if you are using an external clock source because Xin input must be cleared internally to VSS to reduce current leakage.

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Samsung S3F80JB manual SED&R Stop Error Detect and Recovery

Contents

S3F80JB Important Notice Part Programming Model ResetTable of Contents Interrupt Structure Summary Table of Back-Up Mode, Stop Mode, and Reset Status Reset10-3 Timer10-1 10-215-5 Flash Memory User Programming Enable Register Fmusr 15-615-1 15-3Title Number List of Figures10-9 10-510-7 10-812-5 17-3 Typical Low-Side Driver Sink Characteristics17-6 Typical High-Side Driver Source Characteristics 12-218-4 18-3 Typical Low-Side Driver Sink Characteristics18-6 Typical High-Side Driver Source Characteristics 18-2List of Tables Reset Condition in Stop Mode When Ipor / LVD Control Bit is18-3 17-317-6 17-13Chapter Address Spaces Chapter ResetChapter Basic Timer and Timer DescriptionRegister Full Register Name Identifier Instruction Full Register Name Mnemonic Popud NextNOP POPS3F80JB Microcontroller S3C8/S3F8-SERIES MicrocontrollersCPU FeaturesBlock Diagram 32-pin Block Diagram 32-PIN PackageBlock Diagram 44-pin Block Diagram 44-PIN PackagePIN Assignments Pin Assignment Diagram 32-Pin SOP PackagePIN Assignments S3F80JB44-QFP Pin Descriptions of 32-SOP Circuit 32 Pin Shared Names Pin Descriptions of 44-QFP Circuit 44 Pin Shared Names P3.1 Port with bit-programmable pin. Configurable to Pin Circuit Type 1 Port 0 and Port2 PIN CircuitsPin Circuit Type 2 Port 1, Port4, P3.4 and P3.5 PIN CircuitsPin Circuit Type 3 P3.0 Pin Circuit Type 4 P3.1 10. Pin Circuit Type 6 nRESET Overview Address SpaceProgram Memory Address Space Program MemorySmart Option Smart OptionS3F80JB Address Spaces Register Architecture Summary of S3F80JB Register Type Number of BytesTotal Addressable Bytes 333 Internal Register File Organization Register Page Pointer PP Register page Pointer PPRegister SET Set 1, Set 2, and Prime Area Register Map Prime Register SpaceByte Working Register Areas Slices Working RegistersProgramming TIP Setting the Register Pointers Using the Register PointersR0,R3 #80H RP0 ← 80HR0,R1 ← R0 + R0,R2Bit Register Pair Register Addressing10. Register File Addressing RP1 → C8H-CFH Common Working Register Area C0H-CFHProgramming TIP Addressing the Common Working Register Area ExampleBIT Working Register Addressing 12 -Bit Working Register Addressing 14 -Bit Working Register Addressing 15 -Bit Working Register Addressing Example System and User Stacks Stack OperationsStack Pointers SPL POP RP1 SPL,#0FFH SPL ← FFHPush RP0 Push RP1Addressing Modes Register Addressing Register Addressing Mode RIndirect Register Addressing to Register File Indirect Register Addressing Mode IRIndirect Register Addressing to Program Memory Indirect Register Addressing ModeIndirect Working Register Addressing to Register File LCD Indexed Addressing to Register File Indexed Addressing ModeNext 2 Bits Indexed Addressing ModeIndexed Addressing to Program or Data Memory 10. Direct Addressing for Load Instructions Direct Address Mode DA11. Direct Addressing for Call and Jump Instructions Direct Address Mode12. Indirect Addressing Indirect Address Mode IA13. Relative Addressing Relative Address Mode RA14. Immediate Addressing Immediate Mode IMControl Registers D1H T0CNTD0H T0DATAMapped Registers Register Name Mnemonic Decimal Hex Register Description Format Basic Timer Input Clock Selection Bits Btcon Basic Timer Control Register D3H Set1 Bank0Bit Identifier Reset Value Read/Write Addressing Mode Watchdog Timer Function Enable Bits for System ResetCacon Counter a Control Register F3H Set1 Bank0 Clkcon System Clock Control Register D4H Set1 Bank0 CPU Clock System Clock Selection BitsSubsystem Clock Selection Bits External Reference Selection Bit Cmod Comparator Mode Register E9H Set1 Bank1Comparator Enable Bit Conversion Timer Control BitP2.5 Function Selection Bit Cmpsel Comparator Input Selection Register EBH Set1 Bank1P2.7 Function Selection Bit P2.6 Function Selection BitEMT External Memory Timing Register Note FEH Set1 Bank0 Flags System Flags Register D5H Set1 Bank0 Flash Memory Mode Selection Bits Fmcon Flash Memory Control Register EFH Set1 Bank1Operation stop Operation start auto clear bit Flash Memory User Programming Enable Bits Flash Memory Sector Address High ByteFlash Memory Sector Address Low Byte Interrupt Level 0 IRQ0 Enable Bit Timer 0 Match or Overflow Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or OverflowInterrupt Level 2 IRQ2 Enable Bit Counter a Interrupt Interrupt Level 1 IRQ1 Enable Bit Timer 1 Match or OverflowInstruction Pointer Address Low Byte IPH Instruction Pointer High Byte DAH Set1 Bank0IPL Instruction Pointer Low Byte DBH Set1 Bank0 Instruction Pointer Address High ByteIPR Interrupt Priority Register FFH Set1 Bank0 Level 2 IRQ2 Request Pending Bit Counter a Interrupt IRQ Interrupt Request Register DCH Set1 Bank0Not pending Pending Not pendingLVD Flag 2.3V Indicator Bit Lvdcon LVD Control Register E0H Set1 Bank1VDD ≥ Lvdflag Level VDD Lvdflag Level P0.4/INT4 Mode Selection Bits P0.7/INT4 Mode Selection BitsP0.6/INT4 Mode Selection Bits P0.5/INT4 Mode Selection BitsP0.0/INT0 Mode Selection Bits P0.3/INT3 Mode Selection BitsP0.2/INT2 Mode Selection Bits P0.1/INT1 Mode Selection BitsP0.4 External Interrupt INT4 Enable Bit P0.7 External Interrupt INT4 Enable BitP0.6 External Interrupt INT4 Enable Bit P0.5 External Interrupt INT4 Enable BitP0.4 External Interrupt INT4 Pending Flag Bit P0.7 External Interrupt INT4 Pending Flag Bit see NoteP0.6 External Interrupt INT4 Pending Flag Bit P0.5 External Interrupt INT4 Pending Flag BitP0.4 Pull-up Resistor Enable Bit P0.7 Pull-up Resistor Enable BitP0.6 Pull-up Resistor Enable Bit P0.5 Pull-up Resistor Enable BitP1.4 Mode Selection Bits P1.7 Mode Selection BitsP1.6 Mode Selection Bits P1.5 Mode Selection BitsP1.0 Mode Selection Bits P1.3 Mode Selection BitsP1.2 Mode Selection Bits P1.1 Mode Selection BitsP2.4/INT9 Mode Selection Bits P2.7/INT9 Mode Selection BitsP2.6/INT9 Mode Selection Bits P2.5/INT9 Mode Selection BitsP2.0/INT5 Mode Selection Bits P2.3/INT8 Mode Selection BitsP2.2/INT7 Mode Selection Bits P2.1/INT6 Mode Selection BitsP2.4 External Interrupt INT9 Enable Bit P2.7 External Interrupt INT9 Enable BitP2.6 External Interrupt INT9 Enable Bit P2.5 External Interrupt INT9 Enable BitP2.4 External Interrupt INT9 Pending Flag Bit P2.7 External Interrupt INT9 Pending Flag Bit see NoteP2.6 External Interrupt INT9 Pending Flag Bit P2.5 External Interrupt INT9 Pending Flag BitP2.4 Pull-up Resistor Enable Bit P2.7 Pull-up Resistor Enable BitP2.6 Pull-up Resistor Enable Bit P2.5 Pull-up Resistor Enable BitP3CON Port 3 Control Register EFH Set1 Bank0 Each Function Description and Assignment to P3.0-P3.3 P3CONPort 4 Control Register Selection Bit P3.5 Mode Selection BitsP3.4 Mode Selection Bits P345CON Port345 Control Register E1H Set1 Bank1P4CON Port 4 Control Register F0H Set1 Bank0 P4.4 Mode Selection Bits P4.7 Mode Selection BitsP4.6 Mode Selection Bits P4.5 Mode Selection BitsP4.0 Mode Selection Bits P4.3 Mode Selection BitsP4.2 Mode Selection Bits P4.1 Mode Selection BitsSource page 0 See Note PP Register Page Pointer DFH Set1 Bank0Destination page 0 See Note Source Register Page Selection BitsRegister Pointer 1 Address Value RP0 Register Pointer D6H Set1 Bank0RP1 Register Pointer D7H Set1 Bank0 Register Pointer 0 Address ValueStack Pointer Address Low Byte Stop Control Register Enable BitsSPL Stack Pointer Low Byte D9H Set1 Bank0 Stopcon Stop Control Register FBH Set1 Bank0Tri-State External Interface Control Bit SYM System Mode Register DEH Set1 Bank0Fast Interrupt Enable Bit Global Interrupt Enable BitT0CON- Timer 0 Control Register D2H Set 1 Bank0 T1CON Timer 1 Control Register FAH Set1 Bank0 T2CON Timer 2 Control Register E8H Set1 Bank1 Levels VectorsSources S3C8/S3F8-Series Interrupt Types Interrupt TypesS3F80JB Interrupt Structure S3F80JB Interrupt Structure ROM Vector Address Area Interrupt Vector AddressesInterrupt Priority FCHD8H ENABLE/DISABLE Interrupt Instructions EI, DI SYSTEM-LEVEL Interrupt Control RegistersInterrupt Control Register Overview Function Description Interrupt Processing Control Points Interrupt Function DiagramPeripheral Interrupt Control Registers System Mode Register SYM System Mode Register SYMInterrupt Mask Register IMR Interrupt Mask Register IMRInterrupt Request Priority Groups Interrupt Priority Register IPRInterrupt Priority Register IPR Interrupt Request Register IRQ Interrupt Request Register IRQPending Bits Cleared Automatically by Hardware Pending Bits Cleared by the Service RoutineInterrupt Pending Function Types OverviewInterrupt Source Polling Sequence Interrupt Service RoutinesFast Interrupt Processing Generating Interrupt Vector AddressesNesting of Vectored Interrupts Instruction Pointer IPProgramming Guidelines Procedure for Initiating Fast InterruptFast Interrupt Service Routine Fast Interrupt ProcessingAddressing Modes Data TypesLdcd LDELDC LdedLogic Instructions Bit Manipulation Instructions CPU Control Instructions System Flags Register Flags Flags Register FlagsFlag Descriptions Instruction Set Symbols Instruction SET NotationFlag Notation Conventions Irr Indirect working register pair only @RRp p = 0, 2 Immediate addressing mode #data data =Immediate long addressing mode #data data = range @Rn or @reg reg = 0-255, n =Opcode MAP Lower Nibble HEX Opcode Quick ReferenceDjnz INC NOP Djnz INC NextR1,R2 R2,R1 R1,IMCondition Codes Binary Mnemonic Description Flags Set Condition CodesInstruction Descriptions Dst Src ADC Add with carryFlags Format Bytes CyclesADD Add Logical Flags Unaffected Set if the result is 0 cleared otherwiseAlways cleared to Band Bit BCP Bit Compare BCPOperation Bitc Bit Complement BitcHex Dst Bitr Bit Reset Bitr dst.b Operation dstb ←Format Bits dst.b Operation dstb ← Bits Bit SetBOR BOR Bit orBtjrf Bit Test, Jump Relative on False Example Given R1 = 07HBtjrf SKIP,R1.3 Btjrt SKIP,R1.1 Btjrt Bit Test, Jump Relative on TrueR1,01H.1 R1 = 06H, register 01H = 03H Bxor Bit XORCall Call Procedure Call@SP PCL PCH Complemented No other flags are affected CCF Complement Carry FlagCCF Operation C ← not CCLR Clear CLR dst Operation dst ←00H Register 00H COM COM ComplementINC Skip LD CP CompareCpije Cpije Compare, Increment, and Jump on EqualInstruction Cpijne Compare, Increment, and Jump on Non-EqualCpijne If dst src 0, PC ← PC + RADA Decimal Adjust DAdst Operation dst ← DA dstBits @R1 @R1 ← Leave the value 31 BCD in address 27H @R1 R1,R0R1 ← 3CH + 3CHOpc Dst Examples Given R1 = 03H and register 03H = 10H DEC DecrementDEC Dst Operation ← dstDecw Decw Decrement WordDI Disable Interrupts Operation SYM 0 ←No flags are affected Operation dst ÷ src DIV Divide UnsignedSRP #0C0H Djnz R1,LOOP Djnz Decrement and Jump if Non-ZeroDjnz r,dst Operation r ← r Jump taken No jumpEI Enable Interrupts @SP @IP Enter EnterEnter Operation SP@SP Exit ExitExit Operation IPIdle Idle Idle Operation= 1CH Contents of the destination operand are incremented by oneINC Increment INC dst Operation dst ← dst +Loop Incw RR0 Incw Increment WordIncw Incw RR0Flags ← Flags Iret Interrupt ReturnIret Flags ← @SP PC ↔ IPLabelw JP JumpJR Jump Relative Example Given The carry flag = 1 and Labelx = 1FF7HLabelx → PC = 1FF7H Dst ← src LD Load0AH = 0FFH, R1 = 0AHRegister 31H = 0AH, R0 = 01H, R1 = 0AH R0,00H.2 07H, register 00H 05H LDB Load BitLDB Dst Examples Given R0 = 06H and general register 00H = 05HXL L XL H Addr ModeLDC/LDE Load Memory LDC/LDE dst,src Operation dst ← srcExamples LDC/LDELDCD/LDED dst,src Operation dst ← src LDCD/LDED Load Memory and DecrementInto R8 and RR6 is incremented by one RR6 ← RR6 + LDCI/LDEI Load Memory and IncrementLDCI/LDEI dst,src Operation dst ← src Rr ← rr +LDCPD/LDEPD Load Memory with Pre-Decrement LdcpdOperation rr ← rr LDCPI/LDEPI Load Memory with Pre-Increment LdcpiOperation rr ← rr + LDW Load Word RR IMLLDW RR6,RR4 Cleared Mult Multiply UnsignedMult dst,src Operation dst ← dst ⋅ srcNext Next NextOperation PC ← @ IP When the instruction NOP No OperationNOP Or Logical or POP Pop From Stack POP dst Operation dst ← @SP00H Register 00H 55H, SP = 00FCH Popud dst,src Popud Pop User Stack DecrementingPopui dst,src Popui Pop User Stack Incrementing0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH Push Push To StackPush src Operation SP ← SP SPH = 0FFH, SPL = 0FFHDecremented stack pointer Pushud Push User Stack DecrementingPushud IR ← IRPushui dst,src Operation IR ← IR + Pushui Push User Stack IncrementingRCF Reset Carry Flag RCFFlags Cleared to PC = 101AH, SP = 00FEH RET ReturnRET Operation PC ← @SPSet if the result bit 7 is set cleared otherwise RL Rotate LeftDst 0 ← dst Dst n + 1 ← dst n, n =RLC RLC Rotate Left Through CarryRotation cleared otherwise RR Rotate RightRR dst Operation C ← dst00H Register 00H 2AH, C = RRC Rotate Right Through CarryRRC Dst 7 ← CStatement SB0 Select BankSB0 Operation Bank ←SB1 SB1 Select BankSBC Subtract With Carry Always set toSet otherwise, indicating a borrow Format Bytes Cycles Sets the carry flag to logic one SCF Set Carry FlagSCF Set to No other flags are affectedSRA Shift Right Arithmetic SRA dst00H Register 00H 0CD, C = SRP1 SRP/SRP0/SRP1 Set Register PointerSRP SRP0Stop Stop Stop OperationSUB Subtract SUBSet otherwise indicating a borrow Format Bytes Cycles 00H Register 00H 0E3H Swap Swap NibblesSwap dst Flags Undefined Set if the result is 0 cleared otherwise00H,01H Register 00H = 2BH, register 01H = 02H, Z = TCM Test Complement Under MaskR0,R1 = 0C7H, R1 = 02H, Z = R0,@R1 = 0C7H, R1 = 02H, register 02H = 23H, Z =Operation dst and src Always reset toTM Test Under Mask TMdst,srcWFI Wait For Interrupt WFIOpc 4n 3F XOR Logical Exclusive or XOR7FH System Clock Circuit Clock CircuitsSystem Clock Circuit Diagram Clock Status During POWER-DOWN ModesSystem Clock Control Register Clkcon System Clock Control Register ClkconReset Sources ResetReset Sources of The S3F80JB EIexternal interrupt enableReset Block Diagram of The S3F80JB LVD Reset Reset MechanismExternal Reset PIN Watch DOG Timer ResetInternal Power-On Reset Circuit Internal POWER-ON ResetTiming Diagram for Internal Power-On Reset Circuit External Interrupt Reset Reset Timing Diagram for The S3F80JB in Stop mode by IporSlope of V DD Stop Error Detection & RecoveryVreset Reset SourcePOWER-DOWN Modes Idle ModeIdle Mode Release Block Diagram for Back-up Mode BACK-UP ModeProgramming TIP To Enter Stop Mode Stop ModeUsing LVD to Release Stop Mode Sources to Release Stop ModeUsing nRESET Pin to Release Stop Mode Using Ipor to Release Stop ModeSED&R Stop Error Detect and Recovery System Reset Operation Dec Hardware Reset ValuesDec Hex Timer 1 Data Register High ByteTimer 1 Data Register Low Byte Timer 1 Control RegisterTimer 2 Control Register Timer 2 Counter Register Low ByteTimer 2 Data Register High Byte Timer 2 Data Register Low ByteSED&R IporLVD Stop IporConnect to VSS Recommendation for Unusued Pins← # 0FFH P2PURLD STOPCON,#0A5H Summary Table of BACK-UP MODE, Stop MODE, and Reset StatusSummary of Each Mode Item/Mode Back-up Reset Status Stop Stopcon ← # A5HO Ports P3.0-P3.1 S3F80JB Port Configuration Overview 44-QFPPort Configuration Options Assigned individually as analog input pin for comparatorS3F80JB Port Configuration Overview 32-SOP S3F80JB I/O Port Data Register Format Port Data RegistersPull-up Resistor Enable Registers Port 0 and Port 2 only PULL-UP Resistor Enable RegistersTimer Basic Timer BTBasic Timer Control Register Btcon Basic Timer Control Register BtconBasic Timer Function Description Watch-dog Timer FunctionOscillation Stabilization Interval Timer Function Timer 0 Control Register T0CON Timer 0 Control Register T0CON Timer 0 Function Description Timer 0 Interrupts IRQ0, Vectors FAH and FCHInterval Timer Mode Simplified Timer 0 Function Diagram PWM Mode Pulse Width Modulation ModeSimplified Timer 0 Function Diagram Capture Mode Capture ModeBasic Timer and Timer 0 Block Diagram Main BTCON,#52H Programming TIP Configuring the Basic TimerCLR SYM CLR SPLProgramming TIP Programming Timer ULT,NO200MSSET Bits NO200MSSETT0OVER Iret Timer Timer 1 Capture Interrupt Timer 1 Overflow InterruptSimplified Timer 1 Function Diagram Interval Timer Mode Timer 1 Match InterruptTimer 1 Block Diagram Timer 1 Control Register T1CON Timer 1 Control Register T1CONTimer 1 Registers T1CNTH, T1CNTL, T1DATAH, T1DATAL Counter a Counter a Block Diagram Counter a Control Register Cacon Counter a Control Register CaconCounter a Pulse Width Calculations Method 2 When Caof =Counter a Output Flip-Flop Waveforms in Repeat Mode Through P3.1 Set any value except 00H Programming TIP To generate a one-pulse signal through P3.1CADATAH,# Set 40 ms CADATAL,#13-1 Timer 2 Capture Interrupt Timer 2 Overflow InterruptSimplified Timer 2 Function Diagram Interval Timer Mode Timer 2 Match InterruptTimer 2 Block Diagram Timer 2 Control Register T2CON Timer 2 Control Register T2CONTimer 2 Registers T2CNTH, T2CNTL, T2DATAH, T2DATAL Comparator Comparator Block Diagram for The S3F80JB Comparator Operation Conversion CharacteristicsComparator Mode Register Cmod Comparator Result Register Cmpreg Embedded Flash Memory Interface Flash ROM ConfigurationUser Program Mode Tool Program ModePin No Function Isptm ON-BOARD Programming Sector 15-4 Bit ISP Reset Vector and ISP Sector SizeISP Sector Size Area of ISP Sector ISP Sector SizeFlash Memory Control Registers User Program Mode Flash Memory User Programming Enable Register FmusrFlash Memory Control Register Fmcon Flash Memory Sector Address Register Fmsech Flash Memory Sector Address RegistersSector Erase Sector Configurations in User Program ModeSector Erase Flowchart in User Program Mode Sector Erase Procedure in User Program ModeProgramming TIP Sector Erase Case1. Erase one sector Erasestart SB1 FMUSR,#0A5H SectoreraseBtjrf FLAGS.7,NOCARRY NocarryProgramming Program procedure in user program modeByte Program Flowchart in a User Program Mode 10. Program Flowchart in a User Program Mode Case2. Programming in the same sector Programming TIP Programming Case1 -Byte ProgrammingWRINSECTOR50 FMSECH,#19H WRINSECTOR2LD FMSECH,#01H Call WrbyteNZ,LOOP ReadingProgramming TIP Reading Loop LDCHard Lock Protection Programming TIP Hard Lock ProtectionFMCON,#01100001B LVD Flag LVDResistor String Low Voltage Detect Control Register Lvdcon LOW Voltage Detector Control Register LvdconElectrical Data 4MHz Absolute Maximum Ratings Parameter Symbol Conditions Rating UnitD.C. Electrical Characteristics Parameter Symbol Conditions Min Typ Max UnitOutput Low Leakage Current All input pins except ILIH2 and XoutLeakage Current All output pins Output Low Vout = 0 Leakage Current All output pins Pull-UpMin Typ Max Unit Characteristics of Low Voltage Detect CircuitParameter Symbol Conditions Data Retention Supply Voltage in Stop ModeTypical Low-Side Driver Sink Characteristics P3.1 only Typical High-Side Driver Source Characteristics P3.1 only Typical VDD-VOHVDD=3.3V Stop Mode Release Timing When Initiated by a Reset A.C. Electrical Characteristics 10. Input Timing for External Interrupts Port 0 and Port Oscillator Clock Circuit Conditions Min Typ Max Unit Oscillation CharacteristicsTA = 25 C to + 85 C, VDD = 3.6 When released by a reset 216/f StabilizationWait time TWAIT when released by an interrupt Oscillation Stabilization TimeVDD = 2.0 250 Number of Writing/Erasing FNwe 10,000 100 Data Access TimeSector Erasing Time Chip Erasing TimeElectrical Data 8MHZ VDD = 2.35 V, IOH = 2.2mA P3.0 and P2.0-2.3 TA = 25 C to + 85 C, VDD = 1.95 V to 3.6Fosc = 8 MHz Input High Voltage VDD = 2.35 V, IOH = 6mAVDD = 2.35 V, IOL = 12mA Leakage Current All input pins except ILIH2Leakage Current All input pins except ILIL2 Leakage Current All output pins Pull-Up ResistorsFor Back-Up Mode Low Level Detect Voltage Operating Mode DD = 3.6 MHz crystalIdle Mode DD =3.6 MHz crystal Stop Mode LVD OFF, V DD = 3.6 LVD ON, V DD = 3.6Vddv Typical VDD-VOHVDD=3.3V Typical VDD-VOHVDD=3.3V VDD-VOHVIOHmA 18-8 18-9 18-10 Parameter Symbol Condition Min Typ Max Units Comparator Electrical CharacteristicsTA = -25 C to + 85 C, VDD = 3.6 Flash Erase/Write/Read Voltage Fewrv 18-14 SOP-450A Pin SOP Package DimensionQFP-1010B Programming Socket Adapter Target BoardsTB80JB Target Board TB80JB Target Board ConfigurationIDLE, Stop LED Components Consisting of S3F80JB Target Board Block SymbolsJ1A VCC, GND, SJP# Idle LEDStop LED Pin Connector Pin Assignment for TB80JB Development Tools Suppliers Series In-Circuit EmulatorOTP/MTP Programmer GW-PRO2OTP/MTP Programmer Writer SPW2+ SeminixGW-PRO2 Customer sample Risk order For what kind of product will you be using this order?Product description Package Marking Check OneDelivery Date s Quantity Comments Signatures Risk Order InformationCustomer Risk Order Agreement Order Quantity and Delivery ScheduleFlash Application Notes VDD S3F80JB Important Note S3F80JB/9 is needed to nRESET pin = 0GND & Test pin = 1VDD For Serial Programming ModeTiming Diagram For Normal Operating ModeS3F80JB/9 is needed to nRESET pin = 1VDD & Test pin = 0GND When nRESET pin = 1VDD & Test pin = 0GND¾ When S3F80JB When Test PIN = 1VDD¾ When S3F80J9