Texas Instruments TMS380C26 specifications Suds, Sdtack, Slds

TMS380C26

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SPWS010A±APRIL 1992±REVISED MARCH 1993

Terminal Functions (continued)

= L)

System Interface ± Motorola Mode (SI/M

PIN NAME

NO.

I/O

DESCRIPTION

Upper

Data Strobe (see Note 3). This pin

serves as the active-low upper data strobe.

This pin is an input during DIO and an output during DMA.

SRD/

SUDS

61

I/O

H

=

Not valid data on SADH0-SADH7 lines.

L

=

Valid data on SADH0-SADH7 lines.

System Data Transfer Acknowledge (see Note 3). The purpopse of this signal is to indicate to the bus

master that a data transfer is complete. This signal is internally synchronized to SBCLK. During DMA

cycles, it must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state.

SRDY/

SDTACK

60

I/O

This signal is an output when the TMS380C26 is selected for DIO, and an input otherwise.

H

=

System bus NOT ready.

L

=

Data transfer is complete; system bus is ready.

System Reset. This input is activated to place the adapter into a known initial state. Hardware reset

will put most of the TMS380C26 output pins into a high-impedance state and place all blocks into the

reset state.

SRESET

25

IN

H

=

No system reset.

L

=

System reset.

System Register Select. These inputs select the word or byte to be transferred during a system DIO

SRSX

28

access. The most significant bit is SRSX and the least significant bit is SRS1 (see Note 1).

SRS0

27

IN

SRS1

26

MSb

LSb

Register Selected = SRSX

SRS0

SRS1

Bus Error. Corresponds to the bus error signal of the 68000 microprocessor. It is internally

synchronized to SBCLK. This input is driven low during a DMA cycle to indicate to the TMS380C26

SRS2/SBERR

33

IN

that the cycle must be terminated. See Section 3.4.5.3 of the TMS380 Second-Generation Token

Ring User's Guide (SPWU005) for more information (see Note 1).

Lower Data Strobe (see Note 3). This pin is an input during DIO and an output during DMA. This pin

serves as the active-low lower data strobe.

SWR/

SLDS

40

I/O

H

=

Not valid data on SADL0-SADL7 lines.

L

=

Valid data on SADL0-SADL7 lines.

System Extended Address Latch. This output provides the enable pulse used to externally latch the

most significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first

SXAL

42

OUT

cycle of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA

address counter causes a carry-out of the lower 16-bits). Systems that implement parity on

addresses can use SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA

address extension.

108

IN

Reserved. This signal must be left unconnected (see Note 1).

SYNCIN

System Halt/Bus Error Retry. If this signal is asserted along with bus errror

the adapter will

(SBERR),

retry the last DMA cycle. This is the re-run operation as defined in the 68000 specification. The

S8/SHALT

32

IN

BERETRY counter is not decremented by SBERR when SHALT is asserted. See Section 3.4.5.3 of

the TMS380 Second-Generation Token Ring User's Guide (SPWU005) for more information.

NOTES: 1. Pin has an internal pullup device to maintain a high voltage level when left unconnected (no etch or loads). 3. Pin should be tied to VCC with a 4.7-kΩpullup resistor.

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