Texas Instruments Memory bus timing external bus master read from TMS380C26, Macs

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

memory bus timing: external bus master read from TMS380C26

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO.					PARAMETER	MIN	MAX	UNIT
84	Setup time of address on MAX0 and MAX2 before MBCLK1 falling edge, external bus master access					21		ns
85	Hold time of address on MAX0 and MAX2 after MBCLK1 low, external bus master access					0		ns
86	Setup time of valid address before MBCLK1 falling edge, external bus master access					21		ns
87	Hold time of valid address after MBCLK1 low, external bus master access					0		ns
88	Setup time of address high impedance before MBCLK1 falling edge, external bus master read					0		ns
89	Setup time of data/parity valid before MBCLK2 falling edge, external bus master read					1.5tM ± 17²		ns
90	Hold time of valid data/parity after MBCLK2 low, external bus master read					tM ± 13		ns
91	Setup time of data/parity high impedance before MBCLK2 rising edge, external bus master read					tM ± 9		ns
92	Setup time of MDDIR low before MBCLK2 falling edge, external bus master read					21		ns
93	Hold time of MDDIR low after MBCLK2 low, external bus master read					0		ns
94	Setup time of				low before MBCLK2 falling edge, external bus master read	21		ns
			MACS
95	Hold time of			low after MBCLK2 low, external bus master read		0		ns
		MACS

²This specification has been characterized to meet stated value.

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