Texas Instruments TMS380C26 specifications 80x8x interrupt acknowledge timing ± first Siack pulse

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

80x8x interrupt acknowledge timing ± first SIACK pulse

NO.					PARAMETER	MIN MAX	UNIT
286	Pulse duration,			high between DIO accesses (see Note 21)		55	ns
			SIACK
287	Pulse duration,			low on first pulse of two pulses		62.5	ns
		SIACK

NOTE 21: The ªinactiveº chip select is SIACKin DIO read and DIO write cycles, and SCS is the ªinactiveº chip select in interrupt acknowledge

cycles.

SRD, SWR,

SCS

SIACK

287

First

286

Second

Figure 30. 80x8x Interrupt Acknowledge Timing ± First SIACK Pulse

80x8x interrupt acknowledge timing ± second SIACK pulse

NO.

PARAMETER

MIN MAX

UNIT

255

Delay from

low to

high

15

ns

SRDY

SCS

259²

Hold of SAD high-impedance after

low (see Note 21)

0

ns

SIACK

260

Setup of output data valid before

low

0

ns

SRDY

261²

Delay from

high to SAD high-impedance (see Note 21)

35

ns

SIACK

261a

Hold of output data valid after

high (see Note 21)

0

ns

SIACK

272a

Setup of inactive data strobe high to

no longer high

55

ns

SIACK

273a

Hold of inactive data strobe high after

high

55

ns

SIACK

275

Delay from

high to

high (see Note 21)

35

ns

SIACK

SRDY

Delay from

low in the first DIO access to the SIF register to

low in the immediately

276³

SRDY

SRDY

4000

ns

following access to the SIF

279²

Delay from

high to

high impedance

65

ns

SIACK

SRDY

282a

Delay from

low to

low in a read cycle

35

ns

SDBEN

SRDY

Delay from

low to

low (see TMS380 Second Generation

Token-Ring

282R

SIACK

SDBEN

55

ns

User's Guide, SPWU005, subsection 3.4.1.1.1), provided previous cycle completed

283R

Delay from

high to

high (see Note 21)

35

ns

SIACK

SDBEN

²This specification is provided as an aid to board design.

³This specification has been characterized to meet stated value.

NOTE 21: The ªinactiveº chip select is SIACKin DIO read and DIO write cycles, and SCS is the ªinactiveº chip select in interrupt acknowledge cycles.

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