Texas Instruments TMS380C26 Architecture, Communications processor CP, System interface SIF

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

architecture

The major blocks of the TMS380C26 include the Communications Processor (CP), System Interface (SIF), Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), and the Adapter Support Function (ASF). The functionality of each block is described in the following sections.

communications processor (CP)

The Communications Processor (CP) performs the control and monitoring of the other functional blocks in the TMS380C26. The control and monitoring protocols are specified by the software (downloaded or ROM-based) in local memory. Available protocols include:

•Media Access Control (MAC) software,

•Logical Link Control (LLC) software, (token ring version only), and

•Copy All Frames (CAF) software.

The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for pipelining of instructions. These features enhance the TMS380C26's maximum performance capability to about 4 million instructions per second (MIPS), with an average of about 2.5 MIPS.

system interface (SIF)

The System Interface (SIF) performs the interfacing of the LAN subsystem to the host system. This interface may require additional logic depending on the application. The system interface can transfer information/data using any of these three methods:

•Direct Memory Access (DMA),

•Direct Input/Output (DIO), or

•Pseudo-Direct Memory Access (PDMA).

DMA (or PDMA) is used to transfer all data to/from host memory from/to local memory. DIO's main uses are for loading the software to local memory and for initializing the TMS380C26. DIO also allows command/status interrupts to occur to and from the TMS380C26.

The system interface can be hardware selected for either of two modes by use of the SI/M pin. The mode selected determines the memory organizations and control signals used. These modes are:

•The Intel 80x8x families: 8-, 16-, and 32-bit bus members

•The Motorola 68000 microprocessor family: 16- and 32-bit bus members

The system interface supports host system memory addressing up to 32 bits (32-bit reach into the host system memory). This allows greater flexibility in using/accessing host system memory.

System designers are allowed to customize the system interface to their particular bus by:

•Programmable burst transfers or cycle-steal DMA operations

•Optional parity protection

These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported.

The system interface hardware also includes features to enhance the integrity of the TMS380C26 and the data. These features do the following:

•Always internally maintain odd byte parity regardless if parity is disabled,

•Monitor for the presence of a clock failure.

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