SCS SRSX, SRS0, SRS1 Siack Srnw | Texas Instruments TMS380C26

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

SCS SRSX, SRS0, SRS1

SIACK

SRNW

		Valid
	267	268
	272	273a
	272	273
		273

	272a	286
	272a
SUDS,
SLDS
(see Note A)		273a
		273a
	280	281
	280	281a
		281a
SDDIR	(High)
	282W	283W
SDBEN³
	276	279
	276	275
		275
SDTACK²		255
SDTACK²	HI-Z	HI-Z
	282b	263
	282b	262
		262

SADH0±SADH7,

SADL0±SADL7,HI-Z SPH, SPL

Data

(see Note 36)

HI-Z

²SDTACK is an active-low bus ready signal. It must be asserted before data output.

³When the TMS380C16 begins to drive SDBEN inactive, it has already latched the write date internally. Parameter 263 must be met to the input of the data buffers.

NOTE A: For 68xxx mode, skew between SLDS and SUDS must not exceed 10 ns. Provided this limitation is observed, all events referenced to a data strobe edge use the later occurring edge. Events defined by two data strobes edges, such as parameter 286, are measured between latest and earlier edges.

Figure 38. 68xxx DIO Write Timing

78	POST OFFICE BOX 1443 •HOUSTON, TEXAS
	77251±1443

Image 78

Texas Instruments TMS380C26 SCS SRSX, SRS0, SRS1 Siack Srnw, SDBEN³, SDTACK², SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL

Contents

Network Commprocessor Attached System Bus LAN Subsystem Pinout PIN Quad Flat Pack TOP View Description Block diagram and signal descriptions TMS380C26 Terminal FunctionsPIN Name Description Maxpl MaxphAX1 AX0 AX3 AX2 MOE SresetMreset OUT Mras Prtyen NSELOUT0 NSELOUT1 = H Sbhe Sddir Direction DIO DMA ShrqSintr SRD SWR = Selects 16-bit mode 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note Syncin System Interface ± Motorola Mode SI/M = LSBHE/ Srnw Sbrq Terminal Functions = LSbgr Sirq Suds SdtackSlds Pxtalin FRAQ/TXDNsrt RCVR/RXD Lpbk TXCColl Terminal Functions VSS3 VsslVSS1 VSS2 VSS4 VSS5 VSS6 Architecture Communications processor CPSystem interface SIF Memory interface MIF Protocol handler PH Adapter support function ASF Clock generator CG Adapter-Internal Pointers for Token-Ring² Address Description Adapter-Internal Pointers for Ethernet ² Word Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Byte Transfers SIF Adapter Control Register Sifacl Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value Sifacl Register Bit 8 Areset Ð Adapter Reset Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 10 Boot Ð Bootstrap CP Code Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputs Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable System Psdmaen Swhrq Swhlda Sinten Interrupt Result DMA SHRQ/SBRQ Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit See Note Vload IOL Test measurementHigh Low Output Under Test Reference Periods WhenClkdiv = Oscout MBCLK1² MBCLK2² Signal Function Static signalsTiming parameter symbology Timing parameters Reaches minimum high level 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit HVDDH-RSL 118² Pulse duration High 103 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 NMI 126 Delay time from MBCLK1 no longer low to ValidMreset 121 Hold time Valid after MBCLK1 low Mreset MBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph MaxplMADH0±MADH7 Memory bus timing clocks, MRAS, MCAS, and MAL to Address MADL0±MADL7 Maxph MaxplMromen MAL Address Status Column RowAddress Column Status Maxph Maxpl MADH0±MADH7 Memory bus timing read cycleMcas MOE Maxph Maxpl Address Status Data/Parity MAX0 MAX2 MromenMras Mcas Mbiaen Memory bus timing write cycle MAX2 Mromen Enable AddressMAX0, Address Mras Mcas Mben Memory bus timing TMS380C26 releases control of bus Parameter MIN MBCLK1 MBCLK2 Mben 75a 74aMddir MAL Mbiaen Mbrq Mbgr Setup time High before MBCLK1 rising edge, bus resume Memory bus timing TMS380C26 resumes control of busHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Memory bus timing external bus master read from TMS380C26 MacsHold time Low after MBCLK2 low, external bus master read MBCLK1 MBCLK2 MAX0 MAX2 Maxph Maxpl MADH0±MADH7Mddir Macs Memory bus timing external bus master write to TMS380C26 MAX0, MAX2 Maxph MaxplData/Pty 73a Memory bus timing Dram refresh timingMADL0±MADL7 Mras Mcas Mref 127 128 Xmatch and Xfail timingBit Xmatch Xfail Rclk Token ring Ð ring interface timingParameter MIN TYP MAX Unit Rcvr Drvr Token ring Ð transmitter timing see FigureRclk or Pxtalin 160 159 TXD Ethernet timing of clock signalsEthernet timing of Xmit signals Txen RXC Ethernet timing of RCV signals Ð start of frameCRS RXD 320 321 Ethernet timing of RCV signals Ð end of frameCrshld 322 Ethernet timing of RCV signals Ð no RXC NorxcTXD Txen Data 350TXC TXD JAM 80x8x DIO read timing Sras SCS, SrsxSRS0± SRS2 Sbhe Sdben 80x8x DIO write timing 281a Valid 264 265 268 256267 272a 280 281 282W 283W 276 279 275 282b SRD, SWR SCS Siack 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse 287 First 286 Second Sdben SRDY²HI-Z SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL SRD SWR 80x8x mode bus arbitration timing, SIF takes controlSown SWR Sown Sbbsy Shlda SRD, SWRSADL0±SADL7 SPH, SPL This cycle 208b After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² High TwSCKL ± Sbclk Sras 80x8x mode DMA write timing Slds SADH0±SADL7 SPH, SPL SRD HighSADL0±SADH7 Sddir High 80x8x mode bus arbitration timing, SIF returns control TW or 80x8x mode bus release timingSbrls Sown 208c 68xxx DIO read timing Suds Slds SRS0, SRS1Siack Srnw SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL 68xxx DIO write timing Suds Slds Sdtack SDTACK² SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS Srnw Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack Siack Sdtack SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z 275 282a 255 Sbgr 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High Sbrq Suds Srnw Sberr Sdtack SbbsySAS, Slds SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL On this cycle 208b 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low Suds SAS Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL 68xxx mode DMA write timing Sdben Suds Slds SAS SADL0±SADH7, SADH0±SADL7 SPL, SPH 68xxx mode bus arbitration timing, SIF returns control 240 ² Setup SRNW, SIF HI-Z Sbclk Sbgr SdtackRead HI-Z Write Write Read Sbrls Sown 68xxx mode bus release and error timingSown Sberr Sberr Sdtack Sbclk Sdtack Sberr Shalt Rerun cycle with delayed start²Normal completion with delayed start² TH B TH E Sbclk Sdtack Sberr Shalt Sown Jedec NO. Outline Terminals MIN MAX Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM MO±069±AD Important Notice