Pinout, PIN Quad Flat Pack TOP View | Texas Instruments TMS380C26

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

pinout

The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1.

132-PIN QUAD FLAT PACK

(TOP VIEW)

VDDL

CLKDIV

VSSC

NSELOUT0 PRTYEN

BTSTRP

SIACK

SRESET

SRS1

SRS0

SRSX

SCS

SBRLS

SBBSY

S8/SHALT

SRS2/SBERR

VDDL

SI/M

SINTR/SIRQ SHLDA/SBGR

SDDIR

SRAS/SAS

SWR/SLDS

VSSI SXAL

SALE

SBCLK

SADL7

SADL6

SADL5

SADL4

SADL3

VDD5

		V					V			NMI				EXTINT0				EXTINT1				EXTINT2					EXTINT3			MADL0			MADL1			MADL2			MADL3				MADL4				MADL5				MADL6				MADL7					MAXPL								MBGR					MBGQ				MAXPH				MADH0				MADH1				MADH2				MADH3			V				V					MADH4				MADH5				MADH6				MADH7						MBEN			MOE			V
		V					V			NMI				EXTINT0				EXTINT1				EXTINT2					EXTINT3			MADL0			MADL1			MADL2			MADL3				MADL4				MADL5				MADL6				MADL7					MAXPL			V					MBGR					MBGQ				MAXPH				MADH0				MADH1				MADH2				MADH3			V				V					MADH4				MADH5				MADH6				MADH7						MBEN			MOE			V
			SSL				DD4																																																									SS4																																	SS3				DD3																													SS1

17						16				15			14				13				12					11				10			9			8			7			6				5				4			3				2					1					132					131				130				129				128				127				126				125				124				123				122				121				120						119			118			117
18																																																																																																																																116
19																																																																																																																																115
20																																																																																																																																114
21																																																																																																																																113
22																																																																																																																																112
23																																																																																																																																111
24																																																																																																																																110
25																																																																																																																																109
26																																																																																																																																108
27																																																																																																																																107
28																																																																																																																																106
29																																																																																																																																105
30																																																																																																																																104
31																																																																																																																																103
32																																																																																																																																102
33																																																																																																																																101
34																																																																																																																																100
35																																																																																																																																99
36																																																																																																																																98
37																																																																																																																																97
38																																																																																																																																96
39																																																																																																																																95
40																																																																																																																																94
41																																																																																																																																93
42																																																																																																																																92
43																																																																																																																																91
44																																																																																																																																80
45																																																																																																																																89
46																																																																																																																																88
47																																																																																																																																87
48																																																																																																																																86
49																																																																																																																																85
50																																																																																																																																84
51						52				53			54				55				56					57				58			59			69			61			62				63				64			65				66					67					68					69				70				71				72				73				74				75				76				77				78				79				80						81			82			83

	V						SADL2			SADL1				SADL0				SPL				SHRQ/SBRQ					SBHE/SRNW			SDBEN			SOWN			SRDY/SDTACK			SRD/SUDS				SPH				SADH7				SADH6		V				V					V						SADH5					SADH4				SADH3				SADH2				SADH1				SADH0				TEST5				TEST4				TEST3				TEST2				TEST1				TEST0				XFAIL						XMATCH			V		V
			SS5																																																				SSC					DD6				SS6																																																														DD1				SSL

VSSC

MRAS

MW

MCAS

MAX2

MAX0

MDDIR

VDD2

SYNCIN

OSCIN

VSS2

MROMEN

MACS

MAL

MREF

MBIAEN

VDDL MRESET

MBCLK2

MBCLK1

OSCOUT

RCVR/RXD

RCLK/RXC

NSETOUT1

PXTALIN/TXC VSS1

WRAP/TXEN

DRVR

DRVR

WFLT/COLL NSRT/LPBK

FRAQ/TXD

REDY/CRS

Figure 1. TMS380C26 Pinout

2	POST OFFICE BOX 1443 •HOUSTON, TEXAS
	77251±1443

Image 2

Texas Instruments TMS380C26 specifications Pinout, PIN Quad Flat Pack TOP View

Contents

Network Commprocessor Attached System Bus LAN Subsystem Pinout PIN Quad Flat Pack TOP View Description Block diagram and signal descriptions PIN Name Description TMS380C26Terminal Functions Maxpl MaxphAX1 AX0 AX3 AX2 MOE SresetMreset OUT Mras Prtyen NSELOUT0 NSELOUT1 = H Sbhe Sintr Sddir Direction DIO DMAShrq SRD SWR = Selects 16-bit mode 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note Syncin SBHE/ Srnw System Interface ± Motorola Mode SI/M= L Sbrq Terminal Functions = LSbgr Sirq Slds SudsSdtack Pxtalin FRAQ/TXDNsrt RCVR/RXD Coll LpbkTXC Terminal Functions VSS3 VsslVSS1 VSS2 VSS4 VSS5 VSS6 System interface SIF ArchitectureCommunications processor CP Memory interface MIF Protocol handler PH Adapter support function ASF Clock generator CG Adapter-Internal Pointers for Token-Ring² Address Description Adapter-Internal Pointers for Ethernet ² Word Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Byte Transfers SIF Adapter Control Register Sifacl Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value Sifacl Register Bit 8 Areset Ð Adapter Reset Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 10 Boot Ð Bootstrap CP Code Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputs Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable System Psdmaen Swhrq Swhlda Sinten Interrupt Result DMA SHRQ/SBRQ Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit See Note Vload IOL Test measurementHigh Low Output Under Test Clkdiv = Oscout MBCLK1² MBCLK2² Reference PeriodsWhen Signal Function Static signalsTiming parameter symbology Timing parameters Reaches minimum high level 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit HVDDH-RSL 118² Pulse duration High 103 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 NMI 126 Delay time from MBCLK1 no longer low to ValidMreset 121 Hold time Valid after MBCLK1 low MADH0±MADH7 MresetMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl Mromen MAL Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMADL0±MADL7 Maxph Maxpl Address Status Column RowAddress Column Status Maxph Maxpl MADH0±MADH7 Memory bus timing read cycleMcas MOE Maxph Maxpl Address Status Data/Parity MAX0 MAX2 MromenMras Mcas Mbiaen Memory bus timing write cycle MAX2 Mromen Enable AddressMAX0, Address Mras Mcas Mben Memory bus timing TMS380C26 releases control of bus Parameter MIN Mddir MAL Mbiaen Mbrq Mbgr MBCLK1 MBCLK2 Mben75a 74a Hold time Valid after MBCLK1 low, bus resume Setup time High before MBCLK1 rising edge, bus resumeMemory bus timing TMS380C26 resumes control of bus Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Hold time Low after MBCLK2 low, external bus master read Memory bus timing external bus master read from TMS380C26Macs Mddir Macs MBCLK1 MBCLK2MAX0 MAX2 Maxph Maxpl MADH0±MADH7 Data/Pty Memory bus timing external bus master write to TMS380C26MAX0, MAX2 Maxph Maxpl 73a Memory bus timing Dram refresh timingMADL0±MADL7 Mras Mcas Mref 127 128 Xmatch and Xfail timingBit Xmatch Xfail Rclk Token ring Ð ring interface timingParameter MIN TYP MAX Unit Rcvr Drvr Token ring Ð transmitter timing see FigureRclk or Pxtalin 160 159 TXD Ethernet timing of clock signalsEthernet timing of Xmit signals Txen RXC Ethernet timing of RCV signals Ð start of frameCRS RXD 320 321 Ethernet timing of RCV signals Ð end of frameCrshld 322 TXD Txen Ethernet timing of RCV signals Ð no RXCNorxc Data 350TXC TXD JAM 80x8x DIO read timing Sras SCS, SrsxSRS0± SRS2 Sbhe Sdben 80x8x DIO write timing 281a Valid 264 265 268 256267 272a 280 281 282W 283W 276 279 275 282b SRD, SWR SCS Siack 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse 287 First 286 Second Sdben SRDY²HI-Z SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL SRD SWR 80x8x mode bus arbitration timing, SIF takes controlSown SWR Sown SADL0±SADL7 SPH, SPL Sbbsy ShldaSRD, SWR This cycle 208b After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² High TwSCKL ± Sbclk Sras 80x8x mode DMA write timing Slds SADH0±SADL7 SPH, SPL SRD HighSADL0±SADH7 Sddir High 80x8x mode bus arbitration timing, SIF returns control TW or 80x8x mode bus release timingSbrls Sown 208c 68xxx DIO read timing Suds Slds SRS0, SRS1Siack Srnw SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL 68xxx DIO write timing Suds Slds Sdtack SDTACK² SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS Srnw Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack Siack Sdtack SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z 275 282a 255 Sbgr 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High Sbrq Suds Srnw Sberr Sdtack SbbsySAS, Slds SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL On this cycle 208b 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low Suds SAS Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL 68xxx mode DMA write timing Sdben Suds Slds SAS SADL0±SADH7, SADH0±SADL7 SPL, SPH 68xxx mode bus arbitration timing, SIF returns control 240 ² Setup SRNW, SIF HI-Z Sbclk Sbgr SdtackRead HI-Z Write Write Read Sbrls Sown 68xxx mode bus release and error timingSown Sberr Sberr Sdtack Sbclk Sdtack Sberr Shalt Rerun cycle with delayed start²Normal completion with delayed start² TH B TH E Sbclk Sdtack Sberr Shalt Sown Jedec NO. Outline Terminals MIN MAX Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM MO±069±AD Important Notice