SIF Adapter Control Register Sifacl | Texas Instruments TMS380C26

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

SIF Adapter Control Register (SIFACL)

The SIFACL register allows the host processor to control and to some extent reconfigure the TMS380C26 under software control.

SIFACL Register

Bit # 0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

T

T

T

E

E

E

NSEL

NSEL

S

S

S

Ð

SWHLDA

SWDDIR

SWHRQ

PSDMAEN

ARESET

CPHALT

BOOT

RES0

SINTEN

PEN

OUT0

OUT1

T

T

T

0

1

2

R

R

R

RP ± 0

R ± u

R ± 0

RS ± 0

RW ± 0

RP ± b

RP ± b

R

RW ± 1

RP ± p

RP-0

RP±1

R = Read, W = Write, P = Write during ARESET = 1 only, S = Set Only, ±n = Value after reset

(b = Value on BTSTRP pin, p = Value on PRTYEN pin, u = Indeterminate)

Bits 0-2: TEST (0±2). Value on TEST (0±2) pins.

These bits are read only and always reflect the value on the corresponding device pins. This allows the host S/W to determine the network type and speed configuration. If the network speed and type are software configurable, these bits can be used to determine which configurations are supported by the network hardware.

TEST0	TEST1	TEST2	Description
L	L	H	Reserved
L	H	H	16 Mbps token ring
H	L	H	Ethernet (802.3/Blue Book)
H	H	H	4 Mbps token ring
X	X	0	Reserved

Bit 3: Reserved. Read data is indeterminate.

Bit 4: SWHLDA Ð Software Hold Acknowledge

This bit allows the SHLDA/SBGR pin's function to be emulated from software control for pseudo-DMA.

PSDMAEN	SWHLDA	SWHRQ	RESULT

0 ²	X	X	SWHLDA value in the SIFACL register cannot be set to a one.
1 ²	0	0	No pseudo-DMA request pending.
1 ²	0	1	Indicates a pseudo-DMA request interrupt.
1 ²	1	X	Pseudo-DMA process in progress.

²The value on the SHLDA/SBGR pin is ignored.

Bit 5: SWDDIR Ð Current SDDIR Signal Value

This bit contains the current value of the pseudo-DMA direction. This enables the host to easily determine the direction of DMA transfers, which allows system DMA to be controlled by system software.

0= Pseudo-DMA from host system to TMS380C26.

1= Pseudo-DMA from TMS380C26 to host system.

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Image 26

Texas Instruments TMS380C26 SIF Adapter Control Register Sifacl, Sifacl Register, Bit 4 Swhlda Ð Software Hold Acknowledge

Contents

Network Commprocessor Attached System Bus LAN Subsystem Pinout PIN Quad Flat Pack TOP View Description Block diagram and signal descriptions PIN Name Description TMS380C26Terminal Functions Maxpl MaxphAX1 AX0 AX3 AX2 MOE SresetMreset OUT Mras Prtyen NSELOUT0 NSELOUT1 = H Sbhe Sintr Sddir Direction DIO DMAShrq SRD SWR = Selects 16-bit mode 108 Reserved. This signal must be left unconnected see Note= Selects 8-bit mode see Note Syncin SBHE/ Srnw System Interface ± Motorola Mode SI/M= L Sbrq Terminal Functions = LSbgr Sirq Slds SudsSdtack Pxtalin FRAQ/TXDNsrt RCVR/RXD Coll LpbkTXC Terminal Functions VSS3 VsslVSS1 VSS2 VSS4 VSS5 VSS6 System interface SIF ArchitectureCommunications processor CP Memory interface MIF Protocol handler PH Adapter support function ASF Clock generator CG Adapter-Internal Pointers for Token-Ring² Address Description Adapter-Internal Pointers for Ethernet ² Word Transfers User-Access Hardware Registers³ 68xxx Mode is always 16-bit Byte Transfers SIF Adapter Control Register Sifacl Bits 0-2 Test 0±2. Value on Test 0±2 pinsBit 5 Swddir Ð Current Sddir Signal Value Sifacl Register Bit 8 Areset Ð Adapter Reset Bit 6 Swhrq Ð Current Shrq Signal ValueBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 10 Boot Ð Bootstrap CP Code Bit 14 Ð 15 Nselout 0±1 Ð Network selection outputs Bit 12 Sinten Ð System-Interrupt EnableBit 13 PEN Ð Adapter Parity Enable System Psdmaen Swhrq Swhlda Sinten Interrupt Result DMA SHRQ/SBRQ Sifacl Control for Pseudo-DMA OperationSysteminterrupt SINTR/SIRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen Sinten Parameter Test Conditions MIN TYP MAX Unit Recommended operating conditionsMIN NOM MAX Unit See Note Vload IOL Test measurementHigh Low Output Under Test Clkdiv = Oscout MBCLK1² MBCLK2² Reference PeriodsWhen Signal Function Static signalsTiming parameter symbology Timing parameters Reaches minimum high level 289² ThRST Hold time of DMA size from High Intel mode onlyParameter MIN MAX Unit HVDDH-RSL 118² Pulse duration High 103 VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALTMinimun VDD High Level 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289 NMI 126 Delay time from MBCLK1 no longer low to ValidMreset 121 Hold time Valid after MBCLK1 low MADH0±MADH7 MresetMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl Mromen MAL Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMADL0±MADL7 Maxph Maxpl Address Status Column RowAddress Column Status Maxph Maxpl MADH0±MADH7 Memory bus timing read cycleMcas MOE Maxph Maxpl Address Status Data/Parity MAX0 MAX2 MromenMras Mcas Mbiaen Memory bus timing write cycle MAX2 Mromen Enable AddressMAX0, Address Mras Mcas Mben Memory bus timing TMS380C26 releases control of bus Parameter MIN Mddir MAL Mbiaen Mbrq Mbgr MBCLK1 MBCLK2 Mben75a 74a Hold time Valid after MBCLK1 low, bus resume Setup time High before MBCLK1 rising edge, bus resumeMemory bus timing TMS380C26 resumes control of bus Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Hold time Low after MBCLK2 low, external bus master read Memory bus timing external bus master read from TMS380C26Macs Mddir Macs MBCLK1 MBCLK2MAX0 MAX2 Maxph Maxpl MADH0±MADH7 Data/Pty Memory bus timing external bus master write to TMS380C26MAX0, MAX2 Maxph Maxpl 73a Memory bus timing Dram refresh timingMADL0±MADL7 Mras Mcas Mref 127 128 Xmatch and Xfail timingBit Xmatch Xfail Rclk Token ring Ð ring interface timingParameter MIN TYP MAX Unit Rcvr Drvr Token ring Ð transmitter timing see FigureRclk or Pxtalin 160 159 TXD Ethernet timing of clock signalsEthernet timing of Xmit signals Txen RXC Ethernet timing of RCV signals Ð start of frameCRS RXD 320 321 Ethernet timing of RCV signals Ð end of frameCrshld 322 TXD Txen Ethernet timing of RCV signals Ð no RXCNorxc Data 350TXC TXD JAM 80x8x DIO read timing Sras SCS, SrsxSRS0± SRS2 Sbhe Sdben 80x8x DIO write timing 281a Valid 264 265 268 256267 272a 280 281 282W 283W 276 279 275 282b SRD, SWR SCS Siack 80x8x interrupt acknowledge timing ± first Siack pulse80x8x interrupt acknowledge timing ± second Siack pulse 287 First 286 Second Sdben SRDY²HI-Z SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSddir High SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPL SRD SWR 80x8x mode bus arbitration timing, SIF takes controlSown SWR Sown SADL0±SADL7 SPH, SPL Sbbsy ShldaSRD, SWR This cycle 208b After Sbclk low to guarantee recognition on this cycle212 Delay from Sbclk low to address valid 214 ² High TwSCKL ± Sbclk Sras 80x8x mode DMA write timing Slds SADH0±SADL7 SPH, SPL SRD HighSADL0±SADH7 Sddir High 80x8x mode bus arbitration timing, SIF returns control TW or 80x8x mode bus release timingSbrls Sown 208c 68xxx DIO read timing Suds Slds SRS0, SRS1Siack Srnw SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL 68xxx DIO write timing Suds Slds Sdtack SDTACK² SCS SRSX, SRS0, SRS1 Siack SrnwSDBEN³ SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPL SCS Srnw Sdtack 68xxx interrupt acknowledge cycle timingSCS Siack Siack Sdtack SADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSdben SDTACK² HI-Z 275 282a 255 Sbgr 68xxx mode bus arbitration timing, SIF takes control241 Delay from Sbclk high in TX cycle to High Sbrq Suds Srnw Sberr Sdtack SbbsySAS, Slds SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL On this cycle 208b 68xxx mode DMA read timing237R Delay from Sbclk high in the T2 cycle to Low Suds SAS Sale SADL0±SADH7 SADH0±SADL7 SPH, SPL 68xxx mode DMA write timing Sdben Suds Slds SAS SADL0±SADH7, SADH0±SADL7 SPL, SPH 68xxx mode bus arbitration timing, SIF returns control 240 ² Setup SRNW, SIF HI-Z Sbclk Sbgr SdtackRead HI-Z Write Write Read Sbrls Sown 68xxx mode bus release and error timingSown Sberr Sberr Sdtack Sbclk Sdtack Sberr Shalt Rerun cycle with delayed start²Normal completion with delayed start² TH B TH E Sbclk Sdtack Sberr Shalt Sown Jedec NO. Outline Terminals MIN MAX Jedec plastic leaded quad flat package PQ suffix254 0.010 NOM 635 0.025 NOM 76 0.030 NOM MO±069±AD Important Notice