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Texas Instruments TMS380C26 specifications 80x8x DIO read timing

Models: TMS380C26

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TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

80x8x DIO read timing

NO.

PARAMETER

MIN

MAX

UNIT

255

Delay from

low to either

or

high

15

ns

SRDY

SCS

SRD

256

Pulse duration, SRAS high

30

ns

259²

Hold of SAD high-impedance after

low (see Note 21)

0

ns

SRD

260

Setup of SADH0±SADH7, SADL0±SADL7, SPH and SPL valid before

low

0

ns

SRDY

261²

Delay from

or

high to SAD high-impedance (see Note 21)

35

ns

SRD

SCS

261a

Hold of output data valid after

or

high (see Note 21)

0

ns

SRD

SCS

264

Setup of SRSX, SRS0±SRS2,

and

valid to SRAS no longer high (see Note 22)

30

ns

SCS,

SBHE

265

Hold of SRSX, SRS0±SRS2,

and

valid after SRAS low

15

ns

SCS,

SBHE

266a

Setup of SRAS high to

no longer high (see Note 22)

25

ns

SRD

267³

Setup of SRSX, SRS0±SRS2 valid before

no longer high (see Note 21)

15

ns

SRD

268

Hold of SRSX, SRS0±SRS2 valid after

no longer low (see Note 22)

0

ns

SRD

272a

Setup time of

and

high from previous cycle to

no longer high

55

ns

SRD,

SWR,

SIACK

SRD

273a

Hold time of

and

high after

high

55

ns

SRD,

SWR,

SIACK

SRD

275

Delay from

and

or

high to

high (see Note 21)

35

ns

SRD

SWR,

SCS

SRDY

279²

Delay from

and

high to

high impedance

65

ns

SRD

SWR,

SRDY

282a

Delay from

low to

low in a read cycle

35

ns

SDBEN

SRDY

Delay from

low to

low (see TMS380 Second Generation Token-Ring User's Guide,

282R

SRD

SDBEN

55

ns

SPWU005, subsection 3.4.1.1.1), provided previous cycle completed.

283R

Delay from

high to

high (see Note 21)

35

ns

SRD

SDBEN

286

Pulse duration,

high between DIO accesses (see Note 21)

55

ns

SRD

²This specification is provided as an aid to board design.

³ It is the later of SRD and SWR or SCS low that indicates the start of the cycle.

NOTES: 21. The ªinactiveº chip select is SIACKin DIO read and DIO write cycles, and SCS is the ªinactiveº chip select in interrupt acknowledge cycles.

22.In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0 ± SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0±SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters 266a and 264 are irrelevant, and parameter 268 must be met.

POST OFFICE BOX 1443 •HOUSTON, TEXAS	61
77251±1443

Image 61

Texas Instruments TMS380C26 specifications 80x8x DIO read timing

Contents

Attached System Bus LAN Subsystem Network CommprocessorPIN Quad Flat Pack TOP View PinoutDescription Block diagram and signal descriptions Terminal Functions TMS380C26PIN Name Description AX1 AX0 MaxphMaxpl AX3 AX2Mreset OUT SresetMOE MrasNSELOUT0 NSELOUT1 PrtyenSbhe = HShrq Sddir Direction DIO DMASintr SWR SRD= Selects 8-bit mode see Note 108 Reserved. This signal must be left unconnected see Note= Selects 16-bit mode Syncin= L System Interface ± Motorola Mode SI/MSBHE/ Srnw Sbgr Terminal Functions = LSbrq SirqSdtack SudsSlds Nsrt FRAQ/TXDPxtalin RCVR/RXDTXC LpbkColl Terminal Functions VSS1 VSS2 VsslVSS3 VSS4 VSS5 VSS6Communications processor CP ArchitectureSystem interface SIF Protocol handler PH Memory interface MIFClock generator CG Adapter support function ASFAddress Description Adapter-Internal Pointers for Token-Ring²Adapter-Internal Pointers for Ethernet ² ³ 68xxx Mode is always 16-bit User-Access Hardware RegistersWord Transfers Byte TransfersBit 5 Swddir Ð Current Sddir Signal Value Bits 0-2 Test 0±2. Value on Test 0±2 pinsSIF Adapter Control Register Sifacl Sifacl RegisterBit 7 Psdmaen Ð Pseudo-System-DMA Enable Bit 6 Swhrq Ð Current Shrq Signal ValueBit 8 Areset Ð Adapter Reset Bit 10 Boot Ð Bootstrap CP CodeBit 13 PEN Ð Adapter Parity Enable Bit 12 Sinten Ð System-Interrupt EnableBit 14 Ð 15 Nselout 0±1 Ð Network selection outputs System Psdmaen Swhrq Swhlda Sinten Interrupt ResultSysteminterrupt SINTR/SIRQ Sifacl Control for Pseudo-DMA OperationDMA SHRQ/SBRQ Dmadir Sddir Swhlda Swddir Swhrq Psdmaen SintenMIN NOM MAX Unit Recommended operating conditionsParameter Test Conditions MIN TYP MAX Unit See NoteHigh Low Test measurementVload IOL Output Under TestWhen Reference PeriodsClkdiv = Oscout MBCLK1² MBCLK2² Timing parameter symbology Static signalsSignal Function Timing parametersParameter MIN MAX Unit 289² ThRST Hold time of DMA size from High Intel mode onlyReaches minimum high level HVDDH-RSL 118² Pulse duration HighMinimun VDD High Level VDD Sbclk Oscin MBCLK1 MBCLK2 Sreset S8/SHALT103 101 106 104 105 102 107 110 108 109 111 117 118 119 288 289Mreset 126 Delay time from MBCLK1 no longer low to ValidNMI 121 Hold time Valid after MBCLK1 lowMBCLK1 MBCLK2 MAX0 MAX2 ADD/EN Mromen Maxph Maxpl MresetMADH0±MADH7 MADL0±MADL7 Maxph Maxpl Memory bus timing clocks, MRAS, MCAS, and MAL to AddressMromen MAL Address Column RowAddress Status Column StatusMcas MOE Memory bus timing read cycleMaxph Maxpl MADH0±MADH7 Maxph MaxplMras Mcas MAX0 MAX2 MromenAddress Status Data/Parity MbiaenMemory bus timing write cycle MAX0, Address Enable AddressMAX2 Mromen Mras Mcas MbenParameter MIN Memory bus timing TMS380C26 releases control of bus75a 74a MBCLK1 MBCLK2 MbenMddir MAL Mbiaen Mbrq Mbgr Memory bus timing TMS380C26 resumes control of bus Setup time High before MBCLK1 rising edge, bus resumeHold time Valid after MBCLK1 low, bus resume Memory Bus Timing TMS380C26 Resumes Control of Bus Mben Mddir MAL Mbiaen Mbrq Mbgr Macs Memory bus timing external bus master read from TMS380C26Hold time Low after MBCLK2 low, external bus master read MAX0 MAX2 Maxph Maxpl MADH0±MADH7 MBCLK1 MBCLK2Mddir Macs MAX0, MAX2 Maxph Maxpl Memory bus timing external bus master write to TMS380C26Data/Pty MADL0±MADL7 Mras Memory bus timing Dram refresh timing73a Mcas MrefBit Xmatch and Xfail timing127 128 Xmatch XfailParameter MIN TYP MAX Unit Token ring Ð ring interface timingRclk RcvrRclk or Pxtalin Token ring Ð transmitter timing see FigureDrvr 160 159Ethernet timing of Xmit signals Ethernet timing of clock signalsTXD TxenCRS Ethernet timing of RCV signals Ð start of frameRXC RXDCrshld Ethernet timing of RCV signals Ð end of frame320 321 322Norxc Ethernet timing of RCV signals Ð no RXCTXD Txen TXC TXD 350Data JAM80x8x DIO read timing SRS0± SRS2 Sbhe SCS, SrsxSras Sdben80x8x DIO write timing 267 272a 280 281 Valid 264 265 268 256281a 282W 283W 276 279 275 282b80x8x interrupt acknowledge timing ± second Siack pulse 80x8x interrupt acknowledge timing ± first Siack pulseSRD, SWR SCS Siack 287 First 286 SecondSddir High SCS, Srsx SRS0±SRS2 Sbhe Siack SWR SRDSdben SRDY²HI-Z SADH0±SADH7 SADL0±SADL7,HI-ZSPH, SPLSown 80x8x mode bus arbitration timing, SIF takes controlSRD SWR SWR SownSRD, SWR Sbbsy ShldaSADL0±SADL7 SPH, SPL 212 Delay from Sbclk low to address valid 214 ² After Sbclk low to guarantee recognition on this cycleThis cycle 208b High TwSCKL ±Sbclk Sras Slds 80x8x mode DMA write timingSADL0±SADH7 SRD HighSADH0±SADL7 SPH, SPL Sddir High80x8x mode bus arbitration timing, SIF returns control Sbrls Sown 80x8x mode bus release timingTW or 208c68xxx DIO read timing Siack Srnw SRS0, SRS1Suds Slds SDTACK²HI-Z SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSuds Slds Sdtack 68xxx DIO write timingSDBEN³ SCS SRSX, SRS0, SRS1 Siack SrnwSDTACK² SADH0±SADH7 SADL0±SADL7,HI-Z SPH, SPLSCS Siack 68xxx interrupt acknowledge cycle timingSCS Srnw Sdtack Siack SdtackSdben SDTACK² HI-Z SCS, Srsx SRS0, SRS1 Sbhe Siack Srnw SldsSADH0±SADH7 SADL0±SADL7, HI-ZSPH, SPL 275 282a 255241 Delay from Sbclk high in TX cycle to High 68xxx mode bus arbitration timing, SIF takes controlSbgr SbrqSAS, Slds Sberr Sdtack SbbsySuds Srnw SADH0±SADH7 HI-Z SADL0±SADL7 SPH, SPL237R Delay from Sbclk high in the T2 cycle to Low 68xxx mode DMA read timingOn this cycle 208b Suds SASSale SADL0±SADH7 SADH0±SADL7 SPH, SPL Sdben Suds Slds 68xxx mode DMA write timingSADL0±SADH7, SADH0±SADL7 SPL, SPH SAS240 ² Setup SRNW, 68xxx mode bus arbitration timing, SIF returns controlRead HI-Z Write Sbclk Sbgr SdtackSIF HI-Z Write ReadSown Sberr 68xxx mode bus release and error timingSbrls Sown Sberr SdtackNormal completion with delayed start² Rerun cycle with delayed start²Sbclk Sdtack Sberr Shalt TH B TH E Sbclk Sdtack Sberr Shalt Sown254 0.010 NOM 635 0.025 NOM 76 0.030 NOM Jedec plastic leaded quad flat package PQ suffixJedec NO. Outline Terminals MIN MAX MO±069±ADImportant Notice