TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

MBCLK1

MAX0,

MAX2,

MOROMEN

MAXPH,

MAXPL,

MADH0±MADH7,

MADL0±MADL7

MRAS

MCAS

MW

MOE

80

79

80

79

80

79

80

79

80

79

80

79

Figure 13. Memory Bus Timing: TMS380C26 Resumes Control of Bus

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47

77251±1443

 

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Image 47
Texas Instruments specifications Memory Bus Timing TMS380C26 Resumes Control of Bus