Texas Instruments TMS380C26 Memory bus timing read cycle, Mcas MOE, Maxph Maxpl MADH0±MADH7

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

memory bus timing: read cycle

tM is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)

NO.

PARAMETER

MIN

MAX

UNIT

32

Access time from address/enable valid on MAX0, MAX2, and

to valid data/parity

ns

MROMEN

6tM ± 23

33

Access time from address valid on MAXPH, MAXPL, MADH0±MADH7, and MADL0±MADL7

6tM ± 23

ns

to valid data/parity

35

Access time from

low to valid data/parity

4.5tM ± 21.5

ns

MRAS

36

Hold time of valid data/parity after

no longer low

0

ns

MRAS

37²

Hold time of address high impedance on MAXPH, MAXPL, MADH0±MADH7

and

2tM ±10.5

ns

MADL0±MADL7 after MRAS high (see Note 13)

38

Access time from

low to valid data/parity

3tM ±23

ns

MCAS

39

Hold time of valid data/parity after

no longer low

0

ns

MCAS

40²

Hold time of address high impedance on MAXPH, MAXPL, MADH0±MADH7,

and

2tM ±13

ns

MADL0±MADL7 after MCAS high (see Note 13)

41

Delay time from

no longer high to

low

tM +13

ns

MCAS

MOE

42²

Setup time of address/status high impedance on MAXPH, MAXPL, MADL0±MADL7, and

0

ns

MADH0±MADH7 before MOE no longer high

43

Access time from

low to valid data/parity

2tM ± 25

ns

MOE

44

Pulse duration

low

2tM ± 9

ns

MOE

45

Delay time from

low to

no longer low

3tM ± 9

ns

MCAS

MOE

46

Hold time of valid data/parity in after

no longer low

0

ns

MOE

47²

Hold time of address high impedance on MAXPH, MAXPL, MADH0±MADH7,

and

2tM ± 15

ns

MADL0±MADL7 after MOE high (see Note 13)

48²

Setup time of address/status high impedance on MAXPH, MAXPL, MADL0±MADL7, and

0

ns

MADH0±MADH7, before MBEN no longer high

48a²

Setup time of address/status high impedance on MAXPH, MAXPL, MADL0±MADL7, and

0

ns

MADH0±MADH7 and before MBIAEN no longer high

49

Access time from

low to valid data/parity

2tM ± 25

ns

MBEN

49a

Access time from

low to valid data/parity

2tM ± 25

ns

MBIAEN

50

Pulse duration

low

2tM ± 9

ns

MBEN

50a

Pulse duration

low

2tM ± 9

ns

MBIAEN

51

Hold time of valid data/parity after

no longer low

0

ns

MBEN

51a

Hold time of valid data/parity after

no longer low

0

ns

MBIAEN

52²

Hold time of address high impedance on

MAXPH,

MAXPL,

MADH0±MADH7,

and

2t

± 15

ns

MADL0±MADL7 after MBEN high (see Note 13)

M

52a²

Hold time of address high impedance on

MAXPH,

MAXPL,

MADH0±MADH7, and

2t

± 15

ns

MADL0±MADL7 after MBIAEN high

M

53

Hold time of MDDIR high after

high, read follows write cycle

1.5tM ± 12

ns

MBEN

54

Setup time of MDDIR low before

no longer high

3tM ± 9

ns

MBEN

55

Hold time of MDDIR low after

high, write follows read cycle

3tM ± 12

ns

MBEN

²This specification has been characterized to meet stated value.

NOTE 13: The data/parity that exists on the address lines will most likely achieve a high-impedance condition sometime later than the rising edge, of MRAS, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read. Hence, the MIN time given represents the time from the rising edge of MRAS, MCAS, MOE, or MBEN to the beginning of the next address, and does not represent the actual high-impedance period on the address bus.

40	POST OFFICE BOX 1443 •HOUSTON, TEXAS
	77251±1443