Texas Instruments TMS380C26 specifications 80x8x DIO write timing

TMS380C26

NETWORK COMMPROCESSOR

SPWS010A±APRIL 1992±REVISED MARCH 1993

PARAMETER MEASUREMENT INFORMATION

80x8x DIO write timing

NO.

PARAMETER

MIN

MAX

UNIT

255

Delay from

low to either

or

high

15

ns

SRDY

SCS

SWR

256

Pulse duration, SRAS high

30

ns

262

Setup of SADH0±SADH7, SADL0±SADL7, SPH, and SPL valid before

or

no longer low

25

ns

SCS

SWR

263

Hold of SADH0±SADH7, SADL0±SADL7, SPH, and SPL valid after

or

high

25

ns

SCS

SWR

264

Setup of SRSX, SRS0±SRS2,

and

to SRAS no longer high (see Note 21)

30

ns

SCS,

SBHE

265

Hold of SRSX, SRS0±SRS2,

and

after SRAS low

15

ns

SCS,

SBHE

266a

Setup of SRAS high to

no longer high (see Note 22)

25

ns

SWR

267²

Setup of SRSX, SRS0±SRS2 before

no longer high (see Note 21)

15

ns

SWR

268

Hold of SRSX, SRS0±SRS2 valid after

no longer low (see Note 22)

0

ns

SWR

272a

Setup time of

and

high from previous cycle to

no longer high

55

ns

SRD,

SWR,

SIACK

SWR

273a

Hold time of

and

high after

high

55

ns

SRD,

SWR,

SIACK

SWR

Delay from

low in the first DIO access to the SIF register to

low in the immediately following

276³

SRDY

SRDY

access to the SIF (see TMS380 Second-Generation Token Ring User's Guide, SPWU005, subsection

3.4.1.1.1)

275

Delay from

or

high to

high (see Note 21)

35

ns

SWR

SCS

SRDY

279§

Delay from

high to

high impedance

65

ns

SWR

SRDY

280

Delay from

low to SDDIR low (see Note 21)

25

ns

SWR

281

Delay from

high to SDDIR high (see note 21)

55

ns

SWR

281a

Hold of SDDIR low after

no longer active (see Note 21)

0

ns

SWR

If SIF register

is

ready (no waiting

0

35

282b

Delay from SDBEN low to SRDY low (see TMS380 Second Generation Token-Ring

required)

ns

User's Guide, SPWU005, subsection 3.4.1.1.1)

If SIF register

is

not ready (waiting

0

4000

required)

282W

Delay from SDDIR low to

SDBEN

low

25

ns

283W

Delay from

or

high to

no longer low

25

ns

SCS

SWR

SDBEN

286

Pulse duration

high between DIO accesses (see Note 21)

55

ns

SWR

²It is the later of SRD and SWR or SCS low that indicates the start of the cycle. ³ This specification has been characterized to meet stated value.

§ This specification is provided as an aid to board design.

NOTES: 21. The ªinactiveº chip select is SIACKin DIO read and DIO write cycles, and SCS is the ªinactiveº chip select in interrupt acknowledge cycles.

22.In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0±SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0±SRS2, and SCS must meet parameter 264. If SRAS is strapped high, then parameters 266a and 264 are irrelevant, and parameter 268 must be met.

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